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24-Bit Sigma-Delta ADC Simplifies ECG/EKG Analog Front-End Design

Summary: This paper introduces the basic working principle of electrocardiogram (ECG), discusses the factors that interfere with the ECG signal, and the difficulties in improving reliability and realizing high-precision electrical characteristics. The industry-standard ECG architecture is a solution using a combination of an analog front end and an ADC. The MAX11040K simultaneous-sampling sigma-delta ADC offers a compelling highlight in that its highly integrated solution eliminates the AFE, saving space and reducing system cost.
Key words: MAX11040K; 24 bit ADC; analog front end; electrocardiogram; instrumentation amplifier

Electrodes are placed on both sides of the heart and against the skin, and an electrocardiograph (ECG or EKG) records changes in the ECG signal over time. ECG shows the pressure difference between electrode pairs that represent myocardial activity. The heart rate signal is indicated on the Display, which is convenient for doctors to diagnose weak signals in different parts of the myocardium.
The amplitude of the actual ECG signal is only a few millivolts and the frequency does not exceed a few hundred hertz. ECG measurement faces many challenges: on the one hand, the 50 Hz to 60 Hz capacitive coupling interference from the ECG main power supply is stronger than the useful signal; offset and reduce common-mode rejection; in addition, it also addresses contact noise and interference from electromagnetic sources.
In most designs, the analog front end (AFE) is used to extract these signals, amplify and filter the signals, and then use a 12-bit or 14-bit ADC for data acquisition. This article presents the main AFE components of the ECG system and provides a highly integrated design solution, the MAX11040K 24-bit simultaneous sampling Σ-Δ ADC. The MAX11040K provides the circuitry required for this application, eliminating the need for the AFE.
AFE unit
The analog front end includes three main components: amplifier, filter and ADC, as shown in Figure 1. A typical ECG device usually utilizes an AFE for signal amplification, filtering, and then an ADC for data acquisition.

Instrumentation Amplifier (IA)
The main task of an instrumentation amplifier (IA) is to reject common-mode signals (usually 50 Hz/60 Hz interference). ECG applications require a common-mode rejection ratio (CMRR) of 90 dB or more to reject the 50 Hz/60 Hz signal coupled from the power supply before the amplifier circuit. Even with an IA with a high common-mode rejection ratio (CMRR), differences in ECG electrodes or mismatches between skin contact impedances can still cause offset drift and cause CMRR to be lower than desired. Impedance mismatches are primarily due to physical contact between electrodes and skin, perspiration, and muscle movement.
The next factor to consider is the gain of the IA, and care must be taken when setting the gain of the IA to avoid clipping or saturation due to excessive gain.
Also note that the audio signal is not in the same frequency band as the ECG signal. Therefore, typical audio amplifiers and sigma-delta ADCs are not suitable for ECG applications, and these devices have high input-referred noise in the desired signal band.
The IA’s input impedance specification is also important because the ECG measures weak signals. An IA with a high-impedance input is recommended, as lower input impedance results in greater signal attenuation.
high pass filter
Although the initial signal is only on the order of millivolts, it will rise to tens of millivolts after being amplified by 5 or 10 times through the IA. And a signal of this magnitude can only cover a small part of the ADC input range. For example, a 12-bit ADC with a ±4.096 V input range and a least significant bit (LSB) of 2 mV would not have enough resolution to distinguish the signal from sampling noise if it were to directly acquire a signal of tens of millivolts. Therefore, the signal needs to be re-amplified, and the DC drift must also be eliminated. Common AFE circuits use a high-pass filter that feeds unwanted signals (low frequency glitches) as a negative offset (negative feedback) to the IA input.
second stage magnification
After eliminating DC and low frequency interference with IA and high-pass filter, a second stage of amplification is performed to provide additional gain to reach the input range of the ADC. Some designs also add a notch filter for further rejection of 50 Hz/60 Hz.
Low Pass/Anti-Aliasing Filter
The low-pass filter is used to suppress high-frequency interference, and it also acts as an anti-aliasing filter (ie, blocking any signal greater than the Nyquist or 1/2 sampling frequency, to avoid ADC aliasing).
To further reduce the input common-mode signal, ECG designs often also incorporate a first-stage right-leg driver that drives the inverting common-mode signal back to the human body. To ensure patient safety, an op amp and a current-limiting resistor are usually utilized to ensure that a very weak signal source is being driven to the body. This shield is designed to reduce noise coupling from the ECG probe’s signal-carrying signal.
In conclusion, the useful signal in ECG applications is less than 100 mV. This is typically amplified to 2 V to account for offset and common mode signals. Therefore, the AFE must have a 2 V measurement range and can identify signals below hundreds or even tens of microvolts with a sampling rate of around 1 kS/s.
The right ADC can reduce or even eliminate the need for an AFE
Once the AFE design is complete, there are many ADCs that can meet the resolution, speed, and input range requirements of practical applications. However, ADCs with high resolution, high common-mode rejection ratio (CMRR), and other advantages are still prioritized to ensure ECG design requirements.
The MAX11040K simultaneous-sampling, sigma-delta ADC itself has performance specifications that exceed the minimum requirements for this type of application, and can replace most of the system’s functional circuits, even eliminating the AFE, providing a more reliable, smaller package, and simpler design scheme.
Figure 2 shows a simple application of the MAX11040K. The differential input, common-mode rejection ratio of up to 110 dB can effectively suppress 50 Hz/60 Hz power-supply coupled noise, so the MAX11040K can replace the first function of the IA. With its 24-bit resolution and 19-bit noise-free range, the MAX11040K has enough resolution to capture signal changes of a few microvolts. The first-stage amplifier (the second function of the IA), second-stage amplifier, and high-pass filter are omitted. In addition, the device’s ±2.2 V input range is ideal for ECG applications.

The sampling rate of the MAX11040K is 3.072 MHz (oversampling sigma-delta), and the output data rate (ie, the effective sampling rate) is programmable from 64 kS/s to 250 S/s, increasing system flexibility. For small signals, the device features error smoothing, and the use of a sigma-delta ADC architecture also eliminates the need for an antialiasing filter.
Two other features of the MAX11040K are also well suited for ECG applications, namely simultaneous sampling and programmable phase delay. The 12-lead ECG is currently popular in the world, and it is very important to maintain the integrity of the phase. Each MAX11040K provides 4 differential channels, equivalent to 8 probes. The MAX11040K can cascade up to 8 devices, supporting simultaneous sampling of up to 64 channels. Not only can each channel be sampled at the same time, but the phase of each channel can also be programmed (0 to 333 μs delay in 1.33 μs steps).
Test Results for the MAX11040 Solution
Figure 3 shows the block diagram of the MAX11040K evaluation board, which can be used for practical test evaluation. The EV kit contains two MAX11040Ks configured to work with 8-channel simultaneous acquisition. The evaluation board can be plugged into a PC’s USB port, with memory and DSP for easy project development.

In the experiment, copper foil was added to connect the ECG signal, and a 22 kΩ resistor was connected in series between the ADC input and the electrode. The ADC input impedance of 130 kΩ (XIN clock frequency of 24.567 MHz) results in a 75% attenuation of the signal, as shown in Figure 4. The test results are shown in Figure 5. From top to bottom are the time domain display of the original data, the filtered data based on a 32-tap FIR filter based on the Blackman window, and the frequency domain display of the original and filtered data, with a peak at 60 Hz.

The MAX11040K ADC provides ideal specifications without increasing cost. Helps to reduce R&D budget, shorten design time, reduce board area and reduce the component count of the system, while also improving the performance and reliability of the solution.

The Links:   NL2432HC22-25E PM10CNA060