“A flip-flop is a clock-controlled memory element. The flip-flop has a control input signal (CLOCK). The CLOCK signal is that the flip-flop only changes its output state according to the input signal at a specific time. If the flip-flop only accepts input at the transition time of the clock from L to H (H to L), it is said that this kind of flip-flop is triggered by the rising edge (falling edge).
A flip-flop is a clock-controlled memory element. The flip-flop has a control input signal (CLOCK). The CLOCK signal is that the flip-flop only changes its output state according to the input signal at a specific time. If the flip-flop only accepts input at the transition time of the clock from L to H (H to L), it is said that this kind of flip-flop is triggered by the rising edge (falling edge).
Edge D flip-flops are also known as sustain-block edge D flip-flops. When the master-slave flip-flop triggered by the negative edge works, the input signal must be added before the positive edge. If there is a glitch at the input during CP? high, it is possible to make the flip-flop state wrong. The edge trigger allows the input signal to be added immediately before the CP trigger edge. In this way, the time that the input end is disturbed is greatly shortened, and the possibility of being disturbed is reduced.
① is to block the reset line, ② is to maintain the reset line, ③ is to maintain the set line, and ④ is to block the set line. When the flip-flop output is 1, the output remains unchanged by maintaining the set line and blocking the reset line. When the flip-flop output is 0, the output is kept in the reset state by maintaining the set line and blocking the reset line.
There are many types of edge triggers, such as edge triggers using CMOS transmission gates, sustain blocking triggers, and edge triggers using gate transmission delay time. No matter what type of edge flip-flop is used, the sub-state of the flip-flop can only depend on the state of the input signal at the time when the falling edge (or rising edge) of the CP clock pulse arrives, and has nothing to do with the state of the input signal of the flip-flop at other times. . Therefore, the edge type flip-flop greatly improves the reliability of the work and enhances the anti-interference ability. The following uses the edge trigger of the gate circuit transmission delay time as an example to introduce the working principle of the edge trigger.
1) When CP=0, the NAND gates G3 and G4 are blocked, their output Q3=Q4=1, and the state of the flip-flop remains unchanged. At the same time, since the feedback signals of Q3 to Q5 and Q4 to Q6 open these two gates, the input signal D can be received, Q5=D, Q6=Q5=D. ?2) The flip-flop flips when CP changes from 0 to 1. At this time, G3 and G4 are turned on, and the state of their input Q3 and Q4 is determined by the output state of G5 and G6. Q3=Q5=D, Q4=Q6=D. It can be known from the logic function of the basic RS flip-flop that Q=D. ?3) After the flip-flop is flipped, the input signal is blocked when CP=1. This is because after G3 and G4 are turned on, the states of their outputs Q3 and Q4 are complementary, that is, one of them must be 0. If Q3 is 0, the feedback line from G3 output to G5 input will block G5, that is, block G5. D is the path to the basic RS? flip-flop; the feedback line acts to maintain the flip-flop in the 0 state and prevent the flip-flop from changing to the 1 state, so the feedback line is called the 0-hold line and the 1-block line. When Q4 is 0, G3 and G6 are blocked, and the path from the D terminal to the basic RS flip-flop is also blocked. The feedback line from the output of Q4 to G6 plays the role of maintaining the flip-flop in the 1 state, which is called the set-1 maintaining line; the feedback line from the output of Q4 to the G3 input plays the role of preventing the flip-flop from being set to 0, which is called the set-0 blocking line . Therefore, this flip-flop is often referred to as a sustain-blocking flip-flop. In short, the trigger accepts the input signal before the positive edge of the CP, triggers the flip when the positive edge jumps, and the input is blocked after the positive edge. The three steps are completed after the positive edge, so it is called an edge trigger . Compared with the master-slave flip-flop, the edge flip-flop of the same process has stronger anti-interference ability and higher working speed.
1. Circuit structure and working principle
Figure 1 shows an edge JK flip-flop using gate propagation delay time.
Figure 1 Edge JK flip-flop
As can be seen from Figure 1, the circuit consists of two NAND gates G1, G2 and two NAND gates G3, G4. Among them, G1 and G2 form the basic RS flip-flop, and G3 and G4 form the input control circuit. The transmission delay time of the G3 and G4 gates is greater than the inversion time of the basic RS flip-flop.
When CP=0, gates G3 and G4 are locked at high level, and input signals J and K are blocked, that is, R=S=1. At the same time, AND gates A and C are blocked, and the basic RS flip-flop is transmitted through AND gates B and D. At this time, since R=S=1, the basic RS flip-flop state remains unchanged. That is, when CP=0, regardless of the state of the input terminals J and K, the flip-flop remains unchanged.
When CP=1, G3, G4, A, C gates are all opened, and the output of each gate circuit is
It can be seen that when CP=1, regardless of the state of the input terminals J and K, the flip-flop remains unchanged.
When the rising edge of CP arrives (the moment when CP jumps from 0 to 1), gates A and C are first opened. Due to the existence of G3, G4, and transmission delay, the changes of input terminals J and K do not affect G3 and G4. Output, S and R are still 1, and the state of the flip-flop remains the same at this time. After the delay, the flip-flop remains unchanged, and the analysis process is the same as when CP=1. Therefore, the flip-flop remains unchanged when CP is on the rising edge.
When the falling edge of CP arrives (the moment when CP jumps from 1 to 0), since CP is directly added to G1, G2 and the two AND gates A and C outside the gate, gates A and C are first blocked, and their outer The input terminals S and R of the two AND gates B and D need to pass a transmission delay time to become 1 with CP=0.Therefore, before S and R become “1”, the value before the decrease of CP is still maintained, that is,
Before the falling edge of CP arrives, the state of the flip-flop is Qn=0, =1, the input terminal J=1, K=0, and the outputs of G3 and G4 are S=0, R=1 at this time. When the falling edge of CP arrives, each of the two AND gates A and B of the G1 gate has an input of zero, so the output of the G1 gate Qn+1=1 at this time. The output of the G1 gate is fed back to the two inputs of G2, and the two inputs of the AND gate C are both “1”, making the output of the G2 gate. The output of gate G2 is fed back to the input of gate G1. Since the transmission delay time of the G3 gate is long enough, it can be ensured that before the low level of S disappears, the low level has been fed back to the input of the B gate, so that the output of the G1 gate remains high. When the gates of G3 and G4 are delayed, G3 and G4 are blocked, the changes of the input terminals J and K no longer affect the output, and the output S=R=1, so the basic RS flip-flop remains unchanged.
When the input terminals J and K take the values of other states, the analysis method is the same, and the reader is asked to analyze it by himself.
Using the above analysis method, the characteristic table of the edge type JK flip-flop shown in Figure 6-2-8 can be obtained as shown in Table 1. Its logical graphic symbol is shown in Figure 2.
Figure 2 Graphical symbol of edge JK flip-flop
According to the different triggering moments, edge-type flip-flops are divided into two types: rising-edge and falling-edge flip-flops. If the trigger is triggered on the falling edge of the clock pulse CP, it is a falling edge trigger. The circle near the border of the clock pulse CP in the logic symbol indicates the falling edge trigger, and the symbol “”” indicates the edge trigger type. If the flip-flop is triggered on the rising edge of the clock pulse CP, it is a rising edge trigger. In the logic symbol, there is no circle near the border of the clock pulse CP to indicate that the rising edge is triggered.
2. Action characteristics
From the above analysis, it can be seen that the secondary state of the edge flip-flop only depends on the logic state of the input terminal when the falling edge (or rising edge) of the clock pulse CP arrives, and has nothing to do with the state of the input terminal at other times. This is the action characteristic of edge trigger. This feature greatly improves the working stability and anti-interference ability of the flip-flop, and is widely used in digital circuits.
Example 1 In the falling edge JK flip-flop circuit shown in FIG. 3 , the waveform of the known clock pulse CP and the waveforms of the input terminals J and K of the flip-flop are shown in FIG. 3 . Try to draw the waveform of Q at the output of the flip-flop. Let the initial state of the flip-flop be 0.
Figure 3 Example 1
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