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“For large-scale chip design, top-down is a common design flow for 3D integrated circuits. In the three-dimensional layout, the modules that are far apart in the original two-dimensional layout can be placed in the upper and lower layers of chips, so as to be connected in the vertical direction and reduce the length of the wire mesh between the modules.

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Author: Hanqi Yang, DSG Product Engineering Group, Cadence Corporation

For large-scale chip design, top-down is a common design flow for 3D integrated circuits. In the three-dimensional layout, the modules that are far apart in the original two-dimensional layout can be placed in the upper and lower layers of chips, so as to be connected in the vertical direction and reduce the length of the wire mesh between the modules.

Compared with two-dimensional integrated circuits, three-dimensional integrated circuits have the advantages of short wire mesh length, low power consumption, high performance, small package size and good yield.

Large-scale chip design concerns:

How to implement a top-down design process
How to segment a netlist of a two-dimensional integrated circuit to obtain a netlist of a three-dimensional integrated circuit
How to control the number of interconnect signals between different layers of chips
How to plan the position and shape of each module in a 3D layout

The early 3D layout synthesis function of Integrity 3D-IC can help users realize automatic module layout, module shape optimization and netlist segmentation of 3D integrated circuits, quickly explore the 3D layout, and manually work for several weeks in the previous hierarchical design. time was reduced to a few hours.

Today we mainly introduce one of the features of Integrity 3D-IC:

Early 3D Layout Synthesis and Hierarchical Design Methods

1. Integrity 3D-IC Early 3D Layout Synthesis

• Early Floorplan Synthesis (EFS)
• 3D Layout Synthesis
• Tradeoff between net length and number of inter-chip interconnect signals
• Stacking of heterogeneous chips

Early Floorplan Synthesis (EFS)

For large-scale chip design, the layout and routing of each module will be carried out after the RTL starts for a period of time, and the design planning of the top layer of the chip needs to start before the netlist is mature. The top-level planning at this stage is often difficult to create, especially this Each module is constantly being optimized. Therefore, we provide a function of early layout synthesis to automatically and quickly perform module layout, helping users to explore a series of layouts when there are complete netlists, partial netlists, or even no netlist.

Using EFS, the tool can do timing-driven module layout, optimize the shape of the module, and reduce the chip area as much as possible on the premise of satisfying the utilization rate of the module. At the same time, EFS also supports other constraints, including the aspect ratio of the module, the utilization rate, whether feedthrough is allowed, and the width of the routing channel.

3D Layout Synthesis

The increase in the number of chip layers expands the understanding space, making 3D integrated circuit layout planning more difficult.

Based on EFS, Integrity 3D-IC further enhances and introduces the 3D layout synthesis function, which automatically lays out modules in 3D space and adjusts the shape of each module to optimize chip area, wire mesh length and interlayer via data. . In addition, Integrity 3D-IC also supports users to pre-assign modules to a certain layer of chips or pre-place them to a certain location.

The trade-off between net length and number of interconnect signals between chips

Reducing the system net length inevitably increases the number of interconnecting signals between chips. Due to the limitation of Bump/TSV spacing and area, it is necessary to control the number of interconnect signals between chips when doing 3D layout synthesis. Integrity 3D-IC can balance the two well, and through parameter adjustment, it helps users to quickly preview results and explore 3D layout and segmentation.

Stacking of Heterogeneous Chips

Stacking logic chips of different processes can not only meet performance requirements, but also have better yield and lower manufacturing costs. Integrity 3D-IC also supports layout synthesis of heterogeneous 3D integrated circuits, and assigns appropriate processes to different modules.

2. Hierarchical design method

• Hierarchical structure reconstruction
• Timing budget based on logic depth

Hierarchical structure reconstruction

Based on the result of the module layout in 3D space, Integrity 3D-IC will reconstruct the original 2D netlist in a hierarchical structure, and generate two hierarchical structures, Top Die and Bottom Die at the top level of the system, and assign each module to the upper chip and The lower-layer chip, the netlist of the new three-dimensional integrated circuit is obtained. During this process, Integrity 3D-IC can automatically create the Feed Through required to connect the upper-layer chip to the package PKG, and update the series-related timing constraint information, rollover count format files, etc.

Timing budget based on logic depth

In the hierarchical design flow, the timing constraints of the system need to be correctly mapped to the corresponding layers of chips. In the early stage, a fast timing budget can be made based on the clock cycle method, and the appropriate timing constraint files can be allocated to the upper and lower chips according to the specified ratio. To get a more accurate timing budget, you can use the logic depth based timing budget in Integrity 3D-IC. The timing budget based on the logic depth will allocate the timing margin to the chip according to the longest logic path, and allow the user to flexibly set the weight on the combinational logic unit, sequential logic unit, etc. on the logic path, and the fan-out will also are taken into account.

Considering the degrees of freedom of 3D implementation from the beginning of the design provides the best system performance. Integrity 3D-IC enables architects and floor planners to consider the logical and physical distribution of different modules on multiple levels in three-dimensional space from a global perspective. Through Cadence’s powerful hierarchical early floorplanning algorithm, the optimal allocation of different units, modules and IPs at different levels of die is realized, and the advantages of 3D-IC are maximized.