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Enabling Reliable Condition-Based Wired Monitoring for Industry 4.0 – Part 2

In “Enabling Reliable Condition-Based Wired Monitoring for Industry 4.0 – Part 1”, we introduced Analog Devices’ wired interface solution that helps customers reduce design cycles and test time, making industrial CbM solutions more efficient Enter the market quickly. This article discusses various aspects, including choosing the right MEMS accelerometer and physical layer, as well as EMC performance and power supply design. In addition, the three design solutions and performance trade-offs introduced in Part 1 are included. The second part of this article focuses on the physical layer design considerations for the SPI to RS-485/RS-422 design solution presented in the first part.

By: Richard Anslow, Systems Applications Engineer, Analog Devices | Dara O’Sullivan, Systems Applications Engineer


In “Enabling Reliable Condition-Based Wired Monitoring for Industry 4.0 – Part 1”, we introduced Analog Devices’ wired interface solution that helps customers reduce design cycles and test time, making industrial CbM solutions more efficient Enter the market quickly. This article discusses various aspects, including choosing the right MEMS accelerometer and physical layer, as well as EMC performance and power supply design. In addition, the three design solutions and performance trade-offs introduced in Part 1 are included. The second part of this article focuses on the physical layer design considerations for the SPI to RS-485/RS-422 design solution presented in the first part.

Common challenges in implementing wired physical layer interfaces for MEMS include managing EMC reliability and data integrity. However, distributing a clock-synchronized interface like SPI over a long RS-485/RS-422 cable while deploying power and data on the same twisted pair (fake power) presents more challenges. This article discusses the following key issues and provides recommendations for physical layer interface design:

u Management system time synchronization

u Recommended data rate and cable length

u Filter design and simulation for common power and data architectures

u Passive component performance tradeoffs in pseudo power architectures

u Component selection and system design windows

u Experimental measurement

Time synchronization and cable length

When designing an SPI to RS-485/RS-422 link, cables and components can affect system clock and data synchronization. When traveling in a long cable, the SCLK signal will have a propagation delay in the cable, about 400ns to 500ns for a 100-meter cable. For MOSI data transfer, MOSI and SCLK are delayed by the cable for the same amount of time. However, the data sent from the slave MISO to the master has twice the propagation delay and is therefore no longer synchronized to SCLK. The maximum possible SPI SCLK is based on system propagation delay settings, including cable propagation delays, and master and slave component propagation delays.

Figure 1 shows how system propagation delays can cause inaccurate SPI MISO sampling on the SPI master. For systems without RS-485/RS-422 cables, MISO data and SPI SCLK are synchronized with low or no delay. For systems with cables, there is a system propagation delay between the MISO data on the SPI slave and the SPI SCLK, as shown by tpd1 in Figure 1. There are two system propagation delays for MISO data back to the host, as shown by tpd2. Inaccurate data sampling occurs when data is shifted right due to cable and component propagation delays.

Figure 1. MISO data and SPI SCLK synchronization with and without long RS-485/RS-422 cables.

To prevent inaccurate MISO sampling, shorten the cable length, lower the SPI SCLK, or implement a SPI SCLK compensation scheme (clock phase skew) in the host controller. In theory, the system propagation delay should be less than 50% of the SCLK clock period for error-free communication; in practice, a system delay limit of 40% of SCLK can be determined as a general rule.

Figure 2 provides SPI SCLK and cable length guidelines for the two SPI to RS-485/RS-422 designs described in Section 1.1. This non-isolated design uses ADI’s small RS-485/RS-422 devices (ADM3066E and ADM4168E) with high-speed EMC robustness. This isolation design also features Analog Devices’ iCoupler® signal and power isolation ADuM5401 device, which provides improved EMC robustness and noise immunity for SPI to RS-485/RS-422 links. This design increases the system propagation delay, making it impossible to operate at higher SPI SCLK rates. When traveling in longer cables (over 30 meters), increased isolation is strongly recommended to help eliminate the effects of ground loops and EMC events such as electrostatic discharge (ESD), electrical fast transients (EFT), and interference with data High voltage surges coupled by transmission cables. When the cable length reaches or exceeds 30 meters, the SPI SCLK and cable length performance is similar for isolated and non-isolated designs, as shown in Figure 2.

Figure 2. SPI SCLK and cable length guidelines for isolated and non-isolated designs.

False power background knowledge

Fake power deploys power and data on a single twisted pair, enabling a single-cable solution between master and slave. Deploying data and power on the same cable enables a single-connector solution on edge sensor nodes where space is limited.

Power and data are distributed on a single twisted pair through an Inductor-capacitor network, as shown in Figure 3. The high-frequency data is coupled to the data line through a series capacitor, which protects the RS-485/RS-422 transceiver from the DC bus voltage, as shown in Figure 3a. Figure 3 shows the power supply connected to the host controller through the inductor connected to the data line. As shown in Figure 3b, the 5V DC supply biases the AC data bus. In Figure 3c, the current path is shown as an IPWR between the slave and the master, using the inductance on the slave sensor node based on condition monitoring (CbM) at the far end of the cable to draw power from the line.

Figure 3. AC and DC voltage levels at the phantom power physical layer.

high pass filter

In this article, it is assumed that a dummy power supply inductor capacitor network is deployed into two cables, which deploys the RS-485/RS-422 conversion of the SPI MISO signal. Figure 4 depicts the master and slave SPI to RS-485/RS-422 design, and the false supply filter circuit for the SPI MISO data lines. The filter circuit uses a high-pass cable, so it is required that the transmitted data signal cannot contain DC content or very low frequency content.

Figure 4. SPI to RS-485/RS-422 design and false power filter circuit.

A second-order high-pass filter circuit is shown in Figure 5, which is a simplified demonstration of Figure 4. The voltage output of the RS-485/RS-422 transmitter is labeled VTX, and R1 has a 15Ω output resistance. R2 is 30 kΩ, the standard input resistance for RS-485/RS-422 receivers. The inductor (L) and capacitor (C) values ​​can be selected to match the desired system data rate.

When choosing inductor (L) and capacitor (C) values, consider the maximum RS-485/RS-422 bus voltage drop and drop time, as shown in Figure 6.Some standards exist, e.g. for single twisted pair Ethernet2, the indicated maximum allowable pressure drop and pressure drop time are shown in Fig. 6a. For some systems, the maximum allowable drop and drop time values ​​may be larger, limited by the signal polarity crossover point, as shown in Figure 6b.

The voltage drop and drop time can be paired with the simulation in Figure 5 to determine the high pass frequency of the system.

For systems with excellent attenuation, the relationship between the high pass filter cutoff frequency and the voltage drop requirement is shown in Equation 1.3

When adding spurious power to an SPI to RS-485/RS-422 communication system, it is clear that the minimum allowable SPI SCLK rate is limited by the spurious power filter components.

In order to achieve reliable communication without bit errors, the lowest SPI SCLK in the worst case needs to be considered, for example, when all SPI MISO sample bits are logic high, as shown in Figure 7. If all MISO sample bits are logic high, this results in a bit data rate lower than the system SPI SCLK. For example, if the SPI SCLK is 2 MHz and all 16 bits are at logic high, the rate of the spurious power LC filter network is equivalent to the SPI MISO bit rate of 125 kHz.

As shown in the Time Synchronization and Cable Length section, longer cable lengths require lower SPI SCLK rates. However, spurious power supplies limit the minimum SPI SCLK rate. Balancing these opposing requirements requires careful selection and characterization of passive filter components, especially the inductor.

Figure 5. Second-order high-pass filter for RS-422 transmit datapath and RS-485/RS-422 receive datapath.

Figure 6. Dropout and dropout time for an RS-422 receiver.

Figure 7. SPI protocol with MISO 16-bit bursts (all at logic high).

Passive Components Selection

There are many parameters to consider when choosing the right power inductor, including adequate inductance, rated/saturation current, self-resonant frequency (SRF), low DC resistance (DCR), and package size. Table 1 provides selected power inductors and parameters.

The current rating needs to meet or exceed the total current requirement of the remotely powered MEMS sensor node, and the saturation current rating needs to be greater.

This inductance does not present a high impedance to the AC data above its SRF, and after a certain point, it begins to exhibit a capacitive impedance characteristic. The inductor SRF is chosen to limit the maximum SPI SCLK used on the SPI to RS-485/RS-422 physical layer, as shown in Figure 1. When used on long cables, the SRF inductance may not be exposed; for example, the 11 MHz SPI SCLK rate (SRF with part number 744043101) may not be achieved when the cable exceeds 10 meters. In other cases, the inductive SRF may reach lower SPI SCLK rates (2.4 MHz, 1.2 MHz) when running on long cables. As mentioned earlier, the inductor also limits the minimum allowable SCLK rate when used in a dummy power filter network.

Larger value inductors are available in a 12.7 mm × 12.7 mm package, and smaller value inductors are available in a 4.8 mm × 4.8 mm package.

Table 2 shows that there are physical constraints (internal windings), etc., when balancing these opposing requirements to minimize inductor size.

Table 1. Selected Power Inductor Parameters

Product number

L (µH)



Frequency (SRF) (MHz)

DC Resistance (DCR)


Package size (mm)






4.8 × 4.8






8.0 × 8.0






7.8 × 7.0






7.8 × 7.8






10 × 10






12.7 × 12.7

Table 2. Power Inductors – Limitations on Package Size


Impact on package size

high enough inductance

The higher the inductance value, the more internal windings and the larger the package size.

higher SRF

The higher the SRF, the fewer internal windings and the smaller the package size.

Higher rated and saturation current

Fewer internal windings but larger package size.

low DCR

To achieve a lower DCR, the cable needs to be thicker and less winding.

When selecting the proper DC voltage isolation capacitor, limiting factors include transient overvoltage rating and DC voltage rating. The DC voltage rating needs to exceed the maximum bus voltage offset, as shown in Figure 3. When a circuit or connector is shorted, the inductor current is unbalanced and dissipated by the terminal impedance. In the event of a short circuit, the DC blocking capacitors need to be rated for peak transient voltages. For example, in low-power systems, where the inductor saturation current is about 1 A, the corresponding DC blocking capacitor is rated at least 50 V DC. 4

System implementation design window and component selection

There are various design constraints when using a clock synchronization interface like SPI over long RS-485/RS-422 cables, while deploying power and data on the same twisted pair (false power), as shown in Figure 8 . The minimum allowable SPI SCLK is set by the dummy power filter element, which is the high-pass filter data on the SPI data line. The maximum SPI SCLK is set by the spurious supply inductor self-resonant frequency (SRF) or the system propagation delay, whichever is lower for the SPI SCLK value.

Figure 8. Design window constraints.

Table 3 provides the recommended inductor and capacitor values, and the corresponding minimum SPI SCLK was determined by simulating Figure 5, using Figure 6 and Equation 1 as a guide. Among them, it is assumed that VDROOP is 99% of VPEAK. The smallest SPI SCLK also considers the worst-case scenario, as shown in Figure 7, where all data burst bits are logic high. The corresponding cable length is estimated according to Figure 2. The maximum SPI SCLK is set by the system propagation delay or the inductor SRF value.

Below is an example calculation.

To determine the maximum SPI SCLK:

u Indicate the cable length required by the system. In this example, we chose to use a 10-meter RS-485/RS-422 cable.

u Use Figure 2 to determine the maximum SPI SCLK that the system will allow. About 2.6 MHz SPI SCLK is used when the cable is 10 meters long. Decrease the maximum SPI SCLK by 10% for LC component tolerance to provide a 2.3 MHz SPI SCLK. The maximum allowable SPI SCLK may also be limited by the SRF of the selected inductor.

To determine the minimum SPI SCLK:

u Consider the SPI protocol, where all bits on the MISO line are at logic high. In this example, we choose to use the 16-bit SPI protocol, where 16-bit SPI MISO data is sampled during a 32 SCLK transient. If all 16 bits are logic high, then the effective bit rate is 2.3 MHz / 32 = 72 kHz.

u According to Figure 5, at VTXWith a square wave on 72 kHz, multiple L and C values ​​can be used to simulate the cable VRXVoltage waveform on the far end. As the cable length increases, the inductance value and the inductance package size increase. The capacitance value will also increase.

The choice of u L and C values ​​is variable, depending on the desired pressure drop setting, as shown in Figure 6. In this example, assume VDROOP = VPEAK × 99%.

u at VTX7 µs T with 100 µH inductor, 3.3 µF capacitor, and 72 kHz square wave onDROOP, where VDROOP = VPEAK × 99%.

u 6 µs to 7 µs TDROOPEquivalent to 2.3 MHz to 2.6 MHz SPI SCLK.

u If a 100 µH (744043101) inductor is selected, the 2.6 MHz SPI SCLK is lower than the 11 MHz inductor SRF.

The PCB area of ​​the components can be minimized if a 100 µH inductor and 3.3 µF capacitor are used. When using larger inductors, such as 1000 µH or 2200 µH, the PCB area of ​​the component can be increased by a factor of 3. The theoretical maximum SPI SCLK is set by the inductor SRF, which is practically impossible, e.g. using 100 µH at 11 MHz in a system without clock compensation (744043101).

Table 3. Various Fake Power Filter Components

L (µH) and part number

C (µF)

Maximum SPI SCLK (MHz)

Set Factor for Maximum SPI SCLK

Minimum SPI SCLK

Maximum RS-485/RS-422 cable length (meters)





system propagation delay







Inductive SRF







Inductive SRF



If a larger inductance is used, such as 2200 µH, the network needs more capacitance and resistance to dampen the system resonance. The additional components are shown in blue and labeled RDAMP (1 kΩ) and CDAMP (47 µF) in Figure 9.

Experimental setup

Figure 10 shows the wired CbM evaluation platform from Analog Devices, hence the name Pioneer 1. This system uses the SPI to RS-485/RS-422 design solution shown in the first section. Pioneer 1 also includes the ADcmXL3021 wide-bandwidth, low-noise, three-axis MEMS accelerometer, which combines high performance and multiple signal processing capabilities to simplify the development of smart sensor nodes in CbM systems. The SPI to RS-485/RS-422 slave sends the ADcmXL3021 SPI output back to the host controller over a 10m cable for vibration data analysis. The SPI to RS-485 design uses a dummy supply 100 µH inductor and 3.3 µF capacitor to minimize the size of the slave interface solution, which measures 26 mm × 28 mm (excluding the interface connector).

Figure 9. Adding more system attenuation to support larger inductive and capacitive filters.

Figure 10. Pioneer 1 Condition Monitoring-Based Wired Evaluation System.

AC data waveform on fake power line

Figure 11 and Table 4 show the voltages measured on the SPI master and slave, and on the RS-485/RS-422 differential voltage bus. These voltages are measured using the example application setup in Figure 10. Analog signals 1 (yellow) and 2 (blue) are the bus voltage differential representing the MISO signal (purple), measured at the SPI slave output. Digital signal 4 (yellow) shows the MISO sampled on the host controller. The MISO signal on the SPI master matches the polarity and phase of the MISO on the SPI slave with no propagation delay.

Table 4. Measured oscilloscope channels and signals


Impact on package size

2 digits (red)

ADcmXL3021 BUSY, measured on the host

3 digits (orange)

ADcmXL3021 MOSI, measured on host

4 digits (yellow)

ADcmXL3021 MISO, measured on host

5 digits (green)

ADcmXL3021 SCLK, measured on the host

6 digits (blue)

ADcmXL3021 CS, measured on mainframe

3 Analog (purple)

ADcmXL3021 MISO, measured on slave

2 Analog (blue)

RS-422 Z pin bus voltage status, corresponding to MISO; differential voltage of Y and Z, corresponding to 3 analog (purple) and 4 digital (yellow)

1 Analog (yellow)

RS-422 Y pin bus voltage status, corresponding to MISO; differential voltage of Y and Z, corresponding to 3 analog (purple) and 4 digital (yellow)

Figure 11. Voltages measured on the SPI master and slave, and on the RS-422 differential voltage bus.

DC correctness on fake power lines

Figure 12 shows the ADcmXL3021 normal mode, which includes the SPI protocol that sends a 16-bit data burst on MISO, followed by an idle period (16 µs minimum) before sending another 16-bit data burst.

In the fake power network, use a 100 µH inductor and a 3.3 µF capacitor:

u At the end of frame (EOF), the RS-485/RS-422 bus voltage decays back to a steady DC state.

u Idle period DC steady state requires differential voltage RS-422 BA > 500 mV to reflect ADcmXL3021 MISO high impedance state and to ensure a logic 0 is available on the ADM4168E transceiver output. As shown in the filter circuit in Figure 4, the correctness of this idle state is ensured if a 500 Ω resistor is used.

u The next start of frame (SOF) will correctly transition from low to high, or stay low, as determined by the MISO data output of the ADcmXL3021.

u The steady state of the RS-485/RS-422 bus during the idle period does not correspond to the edge of the SPI SCLK, so random noise will not affect the SPI MISO data sampling during this period.

In the fake power network, use a 1000 µH inductor and a 4.7 µF capacitor:

u The ADcmXL3021 MISO output is followed by EOF, idle period and SOF in sequence. During the idle period, the bus voltage level will not decay back to the lowest DC steady state of 500 mV. Some voltage level decay may occur, but not to 500 mV.

Figure 12. DC correctness on false power lines.

Wired Evaluation Solutions

Analog Devices has developed the Pioneer 1 wired system evaluation solution to support the ADcmXL3021 three-axis MEMS accelerometer. As described in the Wikipedia guide, the Pioneer 1 evaluation kit can also utilize expansion boards that support the MEMS devices shown in Table 5.

Table 5. Wired Evaluation Solutions for MEMS Sensors


noise density


Range (g)

Bandwidth (Hz)









10, 20, 40









2, 4, 8





0.5, 1, 2, 4





2, 4, 8









2, 4, 8





2, 4, 8, 16




1, 2, 4, 8




2, 4, 8, 16







1.5, 3, 6, 12

1.5, 3, 6, 12






1 Richard Anslow and Dara O’Sullivan. “Enabling Reliable Condition-Based Wired Monitoring for Industry 4.0 – Part 1.” Analog Devices, July 2019.

2 “IEEE 802.3bu-2016 – IEEE Standard for Ethernet – Amendment 8: Physical Layer and Management Parameters for Single Balanced Twisted Pair Ethernet Power Over Data Line (PoDL) Wires.” IEEE, February 2017 .

3 Andy Gardner. “PoDL: Decoupling Network Demonstration.” Linear Technology, May 2014.

4 Andy Gardner. “PoDL Momentary Connectors and Cable Shorts.” Linear Technology, September 2014.

About the Author

Richard Anslow is a systems applications engineer in the Interconnected Motion and Robotics team in the Automation and Energy business unit at Analog Devices. His areas of expertise are condition-based monitoring and industrial communication design. He holds a Bachelor of Engineering and a Master of Engineering from the University of Limerick, Ireland. Contact information:[email protected]