In Electronic systems, connectors used to connect circuit boards and individual modules are not only expensive but also take up valuable space on the circuit boards and systems, and they also reduce product stability.
Lattice has developed an innovative approach that allows system architects and developers to use extremely small, low-power FPGAs to dramatically reduce the number of inter-board and inter-module connectors, increasing system stability while reducing space and cost.
Developers with FPGA design experience can also customize the solution. Even without FPGA design experience, developers can easily and quickly deploy.
Optimize the connection
The vast majority of electronic systems today contain two or more circuit boards and/or modules. (Unless otherwise stated, the terms “circuit board” or “board” hereinafter will by default include “module”.)
A common problem for system designers is connecting circuit boards for data transfer. A common solution is to mount a multi-pin connector on the board and then use multiple harnesses or wires to connect the boards together.
However, the pins of each connector are a potential point of failure, so in addition to adding cost and space, connectors are often a critical factor in the reliability of electronic systems. This means that minimizing board-to-board connections reduces cost, reduces space and improves system stability.
As shown in Figure 1, the communication rates of signals between these boards are relatively low, using general purpose I/O (GPIO) or serial interfaces such as I2C and I2S.
Figure 1. Traditional connectors are expensive, take up space, and reduce system stability
Designers of systems of all kinds—from handheld devices to laptops to industrial controllers—are eager to minimize connector pin counts and wiring between boards.
One-Wire Aggregation: The Advantages of FPGAs
The principle behind Single Wire Aggregation (SWA) is to aggregate multiple signals into a single time division multiplexed (TDM) signal that requires only one cable to travel between boards. One way to achieve this is to create custom application-specific integrated circuits (ASICs) for each product (Figure 2).
Figure 2. Developing a custom ASIC is expensive, time-consuming, and very inflexible
However, custom ASIC solutions have many disadvantages, such as being expensive and time-consuming to develop. To make matters worse, any algorithms and functions they contain are effectively “frozen in the chip,” meaning they can’t adapt to changing needs. For example, the head of sales suddenly announced: “Our largest customer said it needed to replace one of the I2S interfaces with two I2C channels.”
The ideal solution is a low-cost field-programmable gate array (FPGA) such as the iCE40 UltraPlus™ device from Lattice semiconductor (Figure 3).
Figure 3. FPGAs are inexpensive and very flexible
A huge advantage of using FPGAs to implement single-wire aggregation functions is that they are very flexible and can be quickly and easily custom designed to achieve the desired number and type of channels.
FPGA Designers Use iCE40 UltraPlus for Single-Wire Aggregation
There is a statement in the previous paragraph: “FPGA-based single-wire aggregation allows for quick and easy custom design”. This sentence has a premise that it needs to be very familiar with FPGA design.
If you are an FPGA designer, Lattice offers you the industry’s easiest-to-use FPGA development tools. In addition, Lattice offers a full set of reference design resources for its industry-leading iCE40 UltraPlus™ FPGA in a single-wire aggregation solution:
• Source code for an easy-to-modify, parametric single-wire aggregated reference design that runs on the Lattice Radiant design tool
• Free access to Lattice Radiant® design tools
• Related Reference Design User Guides
• One-Wire Aggregate Demo and Development Board
However, not all design teams have FPGA design experience. Fortunately, Lattice also has solutions for non-FPGA designers.
Non-FPGA Designers Use iCE40 UltraPlus for Single-Wire Aggregation
Take an example of a microcontroller (MCU) based system. Certain members of the design team can be proficient in developing software in a language like C or C++ and then run a software compiler, which produces an executable in machine code. The rest of the team simply loads this machine code file into the MCU and doesn’t need to know anything about programming.
Similarly, FPGA developers specialize in describing designs using hardware description languages (HDLs) such as Verilog or VHDL, and then running hardware compilers called logic synthesis engines to generate configuration files from the HDL, often referred to as bitstreams. The rest of the team can load the bitstream into the FPGA without knowing anything about the FPGA design.
The first single-wire aggregation solution for non-FPGA designers offers five pre-synthesized bitstreams (Figure 4). These configurations are the result of analysis of many practical applications and can meet the requirements of various system designs.
Figure 4. Provides a precompiled bitstream with five common configurations
Users can download the “User’s Guide for Bitstream Files” from the Lattice website Single Wire Aggregation Solutions (latticesemi.com/en-US/singlewire). The guide describes how to load a preconfigured bitstream into the iCE40 UltraPlus FPGA.
In addition, Lattice offers free one-line aggregation design services. You can visit Lattice’s Single Wire Aggregate Development Board webpage, fill out the form, and specify the channel combination required for your design, after which the Lattice design team will email you the corresponding bitstream file.
iCE40 UltraPlus FPGA
In order to better illustrate the content of this article, we need to briefly understand the devices that implement single-wire aggregation. The iCE40 UltraPlus FPGA has a flexible logic architecture, 2800 or 5280 4-input look-up tables (LUTs), customizable general purpose I/O (GPIO), up to 80 Kb embedded memory block (EBM) and up to 1 Mb embedded type SRAM.
The iCE40 UltraPlus FPGA enables ultra-low-power advanced processing functions in most applications with a quiescent current as low as 75 uA and an operating current as low as 1-10 mA. In addition, the iCE40 UltraPlus FPGA also offers a variety of packaging options to meet the needs of various applications:
The ultra-small 2.15 x 2.50 mm WLCSP package is optimized for consumer electronics and IoT devices, while the 7 x 7 mm QFN package with 0.5 mm lead pitch meets the needs of cost-optimized applications.
Since the configuration bitstream can be loaded directly into the SRAM-based configuration cell, the iCE40 UltraPlus FPGA can be reprogrammed iteratively. This allows designers to experiment with different designs and bitstreams, ideal for the prototyping stage of a project.
If the SRAM-based iCE40 UltraPlus device is used in the product, the configuration can be loaded via the on-board MCU or from an external SPI flash device.
In addition, the iCE40 UltraPlus FPGA also includes one-time programmable (OTP) on-chip non-volatile configuration memory (NVCM), making it ideal for mass production. After programming the NVCM, the device will automatically, quickly and safely boot from this configuration.
One-Wire Aggregate Demo and Development Board
The SWA demo and development board contains two iCE40 UltraPlus FPGAs. One piece is used as a data generator or data validator, and the other piece is used to implement a single-wire aggregation reference design (as a controller or peripheral).
Figure 5 shows a typical usage scenario for the two development boards. In this case, the development board on the left contains the data generator and 1-wire aggregation controller, and the development board on the right contains the 1-wire aggregation peripheral and data validator.
Figure 5. Block Diagram of Single Wire Aggregation Demonstration and Development Board Configuration
Observe the jumpers in the diagram. If these jumpers are left, the data from the data generator on the left demo board will be fed into the 1-wire aggregation controller reference design, which will aggregate it into a single signal to the right board. The one-wire aggregated peripheral reference design on the demo board on the right will receive the aggregated signal and feed the deaggregated signal to the data validator. Figure 6(a) below shows this process.
a) Case 1 (retain jumper) b) Case 2 (remove jumper)
Figure 6. Two use cases
Summary of Single Line Aggregation Solution Features
As mentioned above, the single-wire aggregation reference design runs on two iCE40 UltraPlus FPGAs, where one FPGA aggregates multiple data streams (such as I2C, I2S, and GPIO) in a time-division multiplexed fashion and sends it to the other FPGA over a single wire, Deaggregate back to the original data stream.
The single-wire communication speed between the two FPGAs is about 7.5 Mbps. The design is also self-configurable—the number of I2C/I2S buses and GPIOs and the length of the 1-wire protocol packets can be adjusted, and the 1-wire protocol between FPGAs has error detection and retry capabilities. A brief overview of the features of this solution is as follows:
• Aggregate up to 7 channels
• Raw data rate of approximately 7.5 Mbps or higher on a single wire
• Variable packet length for efficient use of single-wire bandwidth
• Retransmission in the event of a parity error at the receiver
• Support I2C Fast-mode (400 kbps) and Fast-mode Plus (1 Mbps)
• I2C interrupts can be implemented using GPIO and event-based transfers
• I2S supports a single stereo channel, 48K hz sample rate, up to 32-bit samples, and bidirectional support
Many electronic systems today include multiple circuit boards.In addition, most of these systems use several different types of interfaces (such as I2C, I2S, andGPIO) to collect data from peripherals and sensors and transfer it between boards.
In addition to the problems inherent in routing signals over crowded boards and connectors, board area and system internal space are often at a premium. In addition to adding cost and space, connectors are often the least reliable components in a system.
Lattice has developed an innovative approach for system architects and developers to implement single-wire aggregation using small-footprint, low-cost FPGAs, significantly reducing the number of board-to-board connectors, increasing system stability while reducing System size and cost.
Developers with FPGA design experience can customize the solution. Additionally, developers can quickly and easily deploy even without any FPGA development experience.