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Hardware and software design of 8-core floating-point DSP with dual Gigabit Ethernet interface

Gigabit network interface has the advantages of fast data transmission rate, convenient connection, and plug-and-play, which makes it widely used. With the development of and processors, the data communication rate in many applications exceeds the actual transmission rate of the Gigabit Ethernet port.

Gigabit network interface has the advantages of fast data transmission rate, convenient connection, and plug-and-play, which makes it widely used. With the development of and processors, the data communication rate in many applications exceeds the actual transmission rate of the Gigabit Ethernet port. For example, in A/D sampling, it is necessary to directly store the sampled data of A/D conversion. If the number of A/D conversion bits is 16 bits and the operation is at 100MHz, the actual data volume is 1.6Gbps. In order to achieve high-speed transmission, a higher transmission rate interface, such as PCIe or RapidIO interface, must be used. However, these interfaces do not have a plug-and-play function, and cannot be directly connected with many existing industrial equipment, which limits their application.

DSP (device) has a high operating frequency, and its internal hardware network MAC interface is integrated, and an external physical layer chip can easily realize Gigabit network communication. The multi-core DSP chip can be connected to multiple Gigabit Ethernet ports, so that it can be applied to high-speed data transmission occasions. This paper introduces an embedded dual-gigabit network interface based on the multi-core digital signal processor TMS320C6678, which realizes that a single chip connects two Gigabit network ports. These two network ports can transmit data independently or jointly. Actual data transfer rate.

1 C6678 and its structure

TMS320C6678 is an 8-core floating-point DSP in TI’s multi-core processors. The operating frequency of each core can reach 1.25GHz. Each core can provide 40GMAC fixed-point computing or 20GFLOP floating-point computing capability. A single chip can provide 320GMAC or 160GFLOP. Calculate ability. The on-chip structure of TMS320C6678 is shown in Figure 1.

Each core of TMS320C6678 has 32KB program, 32KB data and 512KB 2-level Cache storage space, and the chip has a 4MB shared SRAM. TMS320C6678 has a DDR3 controller interface, which can be externally connected to DDR3, and the direct addressing range reaches 8GB. TMS320C6678 is equipped with RapidIO, PCIe, F, SPI, I2C bus and other interfaces inside and outside the chip. These interfaces exchange data with each processor through an on-chip high-speed interconnect bus.

The on-chip devices related to the network are shown as the gray modules in the lower right corner of Figure 1. They mainly include two external SGMII interfaces, Ethernet switching and network switching modules, as well as security accelerators and packet accelerators for data management, which can quickly detect data. Check whether the protocol and the protocol follow the network standard, and discard the wrong data directly to reduce the burden on the CPU. In order to speed up the data exchange between the network and the CPU, the on-chip queue manager is used to manage functions such as buffering and distribution of network packets or frames. These data are all read and written using packet DMA, which does not require CPU participation.

Figure 1 Internal structure of TMS320C6678

Other on-chip devices of TMS320C6678 include modules such as PLL, emulation port, semaphore, power management and reset management. The PLL configures the working clock of the CPU and peripherals; the emulation port is used to connect the emulator to monitor the software operation; the semaphore realizes the control of the semaphore in the DSP/BIOS operating system; the power management realizes the control of the current and voltage of the entire chip ;Reset management configuration startup mode, hard reset for full startup, soft reset for partial startup.

2 88E1111 and its structure

There are many network physical layer chips, which are generally compatible with one or more interface standards such as MII, RMII, and SGMII. But TMS320C6678 only provides SGMII interface, so the physical layer chip connected with TMS320C6678 must have SGMII interface. This article uses two pieces of Marvell’s 88E1111 physical layer chip to connect the dual Gigabit network. The on-chip structure of the 88E1111 is shown in Figure 2.

Figure 2 Internal structure of 88E1111

The analog signal with modulated data sent by the network RJ45 interface is converted into a digital signal through A/D conversion, and then after equalization, shaping filtering and decoding in turn, it is transmitted to the MAC chip by the receiving unit to realize data reception. The data sent by the MAC is converted into an analog signal by D/A after being shaped and filtered and sent to the RJ45 interface. In order to reduce the bit error rate, the 88E1111 has modules such as phase-locked loop (PLL), automatic gain control (AGC), timing/phase control, echo cancellation, etc. These modules are all to improve the reliability of data transmission, in different environments or different Under external devices, high-speed and reliable communication is possible. The LED control module in Figure 2 realizes the light Display during data transmission, the MDIO module realizes link establishment and status monitoring, and the clock module provides the working clock.

3 Hardware Design

The hardware design mainly includes the interfaces of TMS320C6678 and two 88E1111, the interface of 88E1111 and RJ45, and the hardware configuration design of 88E1111.

The network module structure of TMS320C6678 is shown in Figure 3. A 3-port Ethernet switch is integrated in the chip, which is responsible for exchanging the data of the two Gigabit Ethernet ports to the host, and at the same time providing switching interrupts to the host. The host can receive and send data in real time through the interrupt. The host configures or monitors the external physical layer chip through the bus, and the configuration and monitoring data are connected to the physical layer chip through the MDIO interface.

Figure 3 TMS320C6678 network module structure

Figure 4 TMS320C6678 and 88E1111 interface TMS320C6678 and two 88E1111 interface circuit shown in Figure 4. TMS320C6678 adopts SGMII (SerialGigabitMediaIndependentInterface) interface, compatible with 10/100/1000M working mode. SGMII is a serial data transceiver method with fewer pin connections. As can be seen from Figure 4, there are actually only two pairs of differential lines for transmitting and receiving, which are respectively connected to the corresponding 88E1111 pins. The read and write clocks are implicitly transmitted on the data and are automatically recognized by the hardware without software involvement.

Figure 4 Interface of TMS320C6678 and 88E1111

MDIO and MDCLK are the data and clock of the internal MDIO module of TMS320C6678, which are used to establish connection between TMS320C6678 and 88E1111. TMS320C6678 can configure 88E1111 through this interface, or read the information of 88E1111. Since the MDIO module interface level of 88E1111 is 2.5V, and the MDIO module interface level of TMS320C6678 is 1.8V, a voltage conversion chip needs to be added between the two. This design uses PCA9306 to realize voltage conversion, and the interface circuit is shown in Figure 5. Show.

Figure 5 Voltage conversion circuit of MDIO interface

It should be noted that since there are two 88E111 chips, the MDIO and MDCLK pins are directly connected to the two chips, and MDIO can control 32 more physical layer chips, and the physical layer chip addresses are 1~32 respectively. The address configuration of 88E1111 is as follows shown in Figure 6.

Figure 6 Hardware configuration of 88E1111

Table 1 is the corresponding configuration information. According to Figure 6 and Table 1, it can be seen that the addresses of the 88E111 are 4 and 8 respectively.

Table 1 Configuration pin settings

4 Software Design

System software design includes hardware initialization, network configuration and data communication process. Figure 7 shows the work flow after TMS320C6678 is reset. First configure a network port, record its status and configure the second network port. As long as one of the two network ports is successfully configured, the EMAC module of the TMS320C6678 will be configured, and the sending and receiving buffer and sending and receiving tasks will be set for the successfully configured network port. After these configurations, the data transmission and reception of the network can be realized. It should be noted that in the user application, it is necessary to consider the failure of the network port configuration. For example, the user application transmits 1.2Gbps data in real time through dual network ports. If the configuration of one network port fails, the application should have a corresponding mechanism to reduce the real-time transmission rate to below 0.8Gbps (the actual transmission rate of a single network port may be lower than 0.8Gbps). The hardware system in this paper can actually transmit 1.5Gbps data without any other task overhead (errors are not considered during the transmission process, and no retransmission is performed).

Figure 7 Data communication process


Communication interfaces with transmission rates exceeding 1 Gbps generally use interface methods such as optical fiber, PCE, and PCIe. In this paper, the dual network port method can reduce equipment requirements and facilitate connection with existing equipment. The multi-core DSP is used to improve the working ability of the processor. In the process of ensuring the transmission of large-capacity data, the processor still has the ability to calculate the data. The dual network port design scheme can make up for the insufficient transmission rate of a single network port, and can reduce the hardware complexity of other interfaces, which is a useful supplement between the two. It has certain application value in embedded devices.