“Sampling in analog-to-digital converters (ADCs) creates aliasing and capacitive kickback issues that designers address with filters and drive amplifiers, but this presents a series of associated challenges. Especially in mid-bandwidth applications, achieving precision DC and AC performance is challenging, and designers ultimately have to lower their system goals.
Sampling in analog-to-digital converters (ADCs) creates aliasing and capacitive kickback issues that designers address with filters and drive amplifiers, but this presents a series of associated challenges. Especially in mid-bandwidth applications, achieving precision DC and AC performance is challenging, and designers ultimately have to lower their system goals.
This article presents a continuous-time sigma-delta ADC that effectively solves sampling problems by simplifying the signal chain. Using this approach eliminates the need for antialiasing filters and buffers, and addresses signal chain offset errors and drift associated with additional components. This in turn reduces solution size, simplifies design, and improves system phase matching and overall delay.
This article also compares continuous-time converters with discrete-time converters and highlights the system benefits and limitations of using continuous-time sigma-delta ADCs.
Data digitization includes two basic processes of sampling and quantization, as shown in Figure 1. Sampling is the first step in which the continuously time variable analog signal x
Figure 1. Data Sampling
The second step is quantization, where these discrete-time sample values are estimated as a finite possible value and represented by a digital code, as shown in Figure 1. This quantization to a finite set of values results in digitization errors known as quantization noise.
The sampling process also causes aliasing, which can be seen with input signal foldback and harmonics around the sample-and-hold clock frequency. The Nyquist criterion requires that the sampling frequency must be at least twice the highest signal frequency. If the sampling frequency is less than twice the maximum analog signal frequency, a phenomenon called “aliasing” will occur.
To understand the meaning of aliasing in the time and frequency domains, first look at the time-domain representation of a single-tone sine wave sampled signal shown in Figure 2. In this example, the sampling frequency fS is not at least 2 times higher than fa, but only slightly higher than the analog input frequency fa, so it does not meet the Nyquist criterion. Note that the actual sample pattern produces an aliased sine wave of lower frequency fS C fa.
The corresponding frequency domain representation for this case is shown in Figure 3.
The Nyquist bandwidth is defined as the spectrum from DC to fS/2. The spectrum is subdivided into an infinite number of Nyquist zones, each 0.5fS wide. In practical applications, the ideal sampler can be replaced by an ADC followed by an FFT processor. The FFT processor only provides output in the range DC to fS/2; that is, the signal or aliasing that occurs in the first Nyquist zone.
If an ideal pulse sampler is used, a single-frequency sine wave of frequency fa is sampled at frequency fS (see Figure 1). Also assume that fS > 2fa. The frequency domain output of the sampler shows that aliasing or mirroring of the original signal occurs around each fS multiple frequency; that is, at |± KfS ± fa| frequencies, K = 1, 2, 3, 4, etc.
Next, we consider signals outside the first Nyquist zone (Fig. 3). The signal frequency is only slightly less than the sampling frequency, as is the case in the time domain representation in Figure 2. Note that even though the signal is outside the first Nyquist zone, its mirror image (or aliasing) fS C fa is still inside this zone. Back to Figure 3. Clearly, if an interfering signal is present at any of the image frequencies fa, it will also be present at fa, resulting in spurious frequency components in the first Nyquist zone.
Solving Challenges for Precision Performance
For high-performance applications, system designers need to address quantization noise, aliasing, and switched-capacitor input sampling issues caused by the sampling process. Two types of precision ADCs are built using switched capacitor-based sampling techniques, the successive approximation register (SAR) and sigma-delta ADCs commonly found in the industry.
In an ideal Nyquist ADC, the LSB size of the ADC will determine the quantization noise brought into the input when the analog-to-digital conversion is performed. These quantization noises are distributed over the fS/2 bandwidth. In order to solve the problem of quantization noise, oversampling is required first, that is, the input signal is sampled at a rate substantially higher than the Nyquist frequency to improve the signal-to-noise ratio (SNR) and resolution (ENOB). During oversampling, the sampling frequency is chosen to be N times the Nyquist frequency (2 × fIN), so the same quantization noise must be distributed over N times the Nyquist frequency. This also relaxes the anti-aliasing filter requirements. The oversampling ratio (OSR) is defined as fS/2fIN, where fIN is the signal bandwidth of interest. In general, oversampling the ADC by a factor of 4 provides an extra bit of resolution, or an additional 6 dB of dynamic range. Increasing the oversampling rate reduces overall noise and increases dynamic range (DR), since oversampling is ΔDR = 10log10 OSR in dB.
Oversampling can be used and implemented with integrated digital filters and decimation. The delta-sigma ADC basic oversampling modulator shapes the quantization noise so that most of it occurs outside the bandwidth of interest, increasing the overall dynamic range at low frequencies, as shown in Figure 4. Then, a digital low-pass filter (LPF) filters out quantization noise outside the bandwidth of interest, and a decimator reduces the output data rate back to the Nyquist rate.
Noise shaping is another technique used to reduce quantization noise. In a sigma-delta ADC, a low-resolution (one- to five-bit) quantizer is used in the loop after the loop filter. The DAC is used as feedback to extract the quantized signal from the input, as shown in Figure 5.
The integrator will accumulate the quantization error, shape the quantization noise to higher frequencies, and then filter it with a digital filter. Figure 6 shows a typical sigma-delta ADC output x[n]the power spectral density (PSD). The noise shaping slope depends on the loop filter order H(z) (see Figure 11) and is (20 × n) dB per decade, where n is the loop filter order. Sigma-delta ADCs achieve in-band high resolution through a combination of noise shaping and oversampling. In-band bandwidth is equal to fODR/2 (ODR stands for output data rate). Higher resolution can be obtained by increasing the order of the loop filter or increasing the oversampling rate.
To address aliasing in high performance applications, higher order antialiasing filters can be used to avoid any amount of aliasing. An anti-aliasing filter is a low-pass filter whose bandwidth limits the input signal and ensures that the signal does not contain frequency components outside the target bandwidth that can be folded back. Filter performance will depend on how close the out-of-band signal is to fS/2 and the amount of attenuation required.
For SAR ADCs, the gap between input signal bandwidth and sampling frequency is not large, so we need to use higher order filters, which require a more complex, higher order filter design with higher power and distortion Big. For example, if a SAR sampling at 200 kSPS has an input bandwidth of 100 kHz, the anti-aliasing filter needs to reject input signals >100 kHz to ensure no aliasing occurs. This requires the use of very high-order filters. Figure 7 shows a steep demand curve.
If you choose to use a 400 kSPS sampling speed to reduce the filter order, you need to reject input frequencies >300 kHz. Increasing the sampling speed will increase the power, and if you achieve double the speed, you will also need double the power. Since the sampling frequency is much higher than the input bandwidth, further increasing the oversampling at the expense of power further relaxes the antialiasing filter requirements.
In a sigma-delta ADC, the input is oversampled with a higher OSR, which relaxes the antialiasing filter requirements because the sampling frequency is much higher than the input bandwidth, as shown in Figure 8.
Figure 9 shows the complexity of AAF in SAR and discrete-time sigma-delta (DTSD) architectures. If we were to use a 100 kHz C3 dB input bandwidth to achieve 102 dB attenuation at the sampling frequency fS, the DTSD ADC would require a second-order anti-aliasing filter; with a SAR ADC to achieve the same attenuation at fS, five order filter.
For the continuous-time sigma-delta (CTSD) ADC, it has inherent attenuation, so we don’t need to use any anti-aliasing filters.
These filters are a challenge for system designers, who must optimize them to provide attenuation within the frequency band of interest, and as much rejection as possible. They also add many other errors, such as offset, gain, phase error, and system noise, which degrade their performance.
Also, high-performance ADCs are inherently differential, so we need to use double the number of passive components. To achieve better phase matching in multi-channel applications, all components in the signal chain must also be matched. Therefore, tighter tolerance components are required.
Switched Capacitor Input
Switched capacitor input sampling depends on the settling time of the capacitor upsampling input, so charging/discharging transient currents are required when switching the sampling switch. This is called input kickback and requires the use of an input driver amplifier that supports these transient currents. Additionally, the requirement to settle the input at the end of the sampling time, and the accuracy of the sampled input determines the performance of the ADC, means that the driver amplifier needs to settle quickly after a kickback event. A high bandwidth driver that supports fast settling and can absorb the kickback of switched capacitor operation is therefore required. In a switched capacitor input, the driver must supply power to the hold capacitor immediately whenever sampling is turned on. This current surge can only be delivered in time if the driver has sufficient bandwidth capability. Due to switching parasitics, there is a kickback on the driver when sampling. If the kickback fails to settle before the next sample, it can cause sampling errors that affect the ADC input.
Figure 10 shows kickback on a DTSD ADC. For example, if the sampling frequency is 24 Mhz, the data signal needs to settle in 41 ns. Because the reference is also a switched capacitor input, a high bandwidth buffer is also required on the reference input pin. These input signal and reference buffers also add noise, degrading the overall performance of the signal chain. In addition, the distortion components of the input signal driver (around the S&H frequency) further increase the antialiasing requirements. For switched capacitor inputs, changes in sampling speed cause changes in input current. This can cause the system to be retuned to reduce gain errors from the driver or previous stage when driving the ADC.
Continuous Time Sigma-Delta ADC
CTSD ADCs are another sigma-delta ADC architecture that utilizes principles such as oversampling and noise shaping, but offers another method of implementing sampling with significant system benefits.
Figure 11 compares the DTSD architecture with the CTSD architecture. As can be seen, the DTSD architecture samples the input before the loop. The loop filter H(z) is discrete in time and implemented using a switched capacitor integrator. The feedback DAC is also based on switched capacitors. Since sampling the input can cause aliasing problems in fS, an anti-aliasing filter is required at the input before sampling the input.
CTSD does not have a sampler on the input, but samples up a quantizer inside the loop. The loop filter achieves time continuity using a continuous time integrator, as does the feedback DAC. As quantization noise is shaped, aliasing due to sampling is shaped. This results in an ADC with almost no sampling aliasing, making it a class of its own.
The sampling frequency of CTSD is fixed, unlike DTSD, where the sampling frequency of the modulator can be easily extended. In addition, CTSD ADCs are less tolerant to jitter than switched capacitor ADCs. Off-the-shelf crystal or CMOS oscillators provide a local low-jitter clock to the ADC, helping to avoid transmitting low-jitter clocks in isolation and reducing EMC.
CTSD has two major advantages, it has inherent aliasing rejection, and provides resistive input for signal and reference.
Inherent anti-aliasing capability
Moving the quantizer into the loop creates inherent aliasing suppression. As shown in Figure 12, the input signal passes through a loop filter before sampling, and the foldback (aliasing) error generated at the quantizer is also removed by this filter. Signal and aliasing errors have the same noise transfer function as the sigma-delta loop, and noise shaping similar to quantization noise is implemented in the sigma-delta architecture. Therefore, the frequency response of the CTSD loop naturally suppresses input signals that are approximately integer multiples of the sampling frequency, acting as an anti-aliasing filter.
It is easier to drive with resistive inputs in the signal and reference inputs than in a sample-and-hold configuration. When a constant resistive input is provided, there is no kickback and the driver can be completely removed. The input is not distorted, as shown in Figure 13. And because the input impedance is constant, there is no need to retune the system for gain errors.
The analog input may be bipolar even if the ADC provides a unipolar supply. Therefore, there is no need to perform level translation between the bipolar front end and the ADC. The DC performance of the ADC may not be the same as when the input resistors now have input common-mode dependent currents and input currents.
The reference load is also resistive to reduce switching kickback, eliminating the need for a separate reference buffer. The resistors for the low pass filter can be on-chip to track with the on-chip resistive load (since they may be the same material) to reduce gain error temperature drift.
CTSD architectures are not new, but megatrends in the industrial and instrumentation markets require DC and AC precision performance at higher bandwidths. Additionally, customers prefer a single platform design for most solutions to help them reduce time to market.
The CTSD architecture has many advantages over other types of ADCs, making it the first choice for many applications such as high-performance audio and cellular mobile phone RF front-ends. These advantages include easier integration and lower power consumption, but more importantly, the use of CTSD can solve several important system problems. The use of CTSD was previously limited to audio/bandwidth and lower dynamic range due to many technical deficiencies. Therefore, the mainstream solution for high precision, high performance/medium bandwidth applications has been high performance Nyquist rate converters such as successive approximation ADCs and oversampling DTSD converters.
However, recent technological breakthroughs by Analog Devices can overcome many of the previous limitations. The AD7134 is the first CTSD-based high precision DC to 400 kHz bandwidth ADC that can achieve higher performance specifications while providing DC accuracy, which in turn addresses several critical system-level issues in high performance instrumentation applications. The AD7134 also integrates an asynchronous sample rate converter (ASRC) that can provide data at different data rates through the CTSD’s fixed sample rate. The output data rate can be independent of the sampling frequency of the modulator, and can ensure the successful use of CTSD ADC to achieve different granularity of throughput. The output data rate can also be flexibly changed at the granular level, allowing users to use coherent sampling.
Signal Chain Advantages of the AD7134
Inherent alias suppression eliminates the need for anti-aliasing filters, thereby reducing component count and enabling smaller solution size. What’s more, performance issues associated with anti-aliasing filters, such as droop, offset, gain error, phase error, and noise in the system, are eliminated.
Low Latency Signal Chain
Anti-aliasing filters can significantly increase the overall delay of the signal chain depending on the rejection needs. Removing the filter completely eliminates this delay and enables precise transitions in noisy CNC loop applications.
Excellent phase matching
Eliminating the need for anti-aliasing filters at the system level greatly improves the phase matching performance of multi-channel systems. Ideal for applications requiring low channel-to-channel mismatch, such as vibration monitoring, power measurement, data acquisition modules, and sonar.
Reliable against interference
The CTSD ADC is immune to any system-level interference, as well as internal IC interference, due to its inherent filtering capabilities. For DTSD ADCs and SAR ADCs, care must be taken to reduce disturbances during ADC sampling. In addition, because of its own filtering function, the power supply line will not be disturbed.
With constant resistive analog and reference inputs, dedicated drivers are completely eliminated. Additionally, all performance-related issues such as offset, gain, phase error, and system noise errors are eliminated.
easy to design
Because the number of design components is greatly reduced, the difficulty of achieving precision performance is greatly reduced. This reduces design time, accelerates time-to-market, simplifies BOM management, and improves reliability.
Eliminates the need for anti-aliasing filters, drivers and reference buffers, resulting in a significant reduction in system board size. An instrumentation amplifier can be used to drive the ADC directly. For the AD7134, since it is only a differential input ADC, a differential in-amp (such as the LTC6373) can be used as the driver. The discrete-time and continuous-time signal chains are compared in Figure 14. Experimental results show that the continuous-time signal chain can save 70% of the area compared to the equivalent discrete-time signal chain, making it ideal for high-density multi-channel applications.
In conclusion, the AD7134 enables easy design-in, greatly reduces system size, simplifies signal chain design, improves system reliability, and shortens overall time-to-market without compromising performance parameters for precision instrumentation applications.