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PCB design skills of op amp circuits that designers must know

Printed circuit board (PCB) routing plays a critical role in high-speed circuits, but it is often one of the last steps in the circuit design process. There are many aspects of high-speed PCB routing, and a great deal of literature has been written on the subject. This paper mainly discusses the wiring problems of high-speed circuits from a practical point of view. The main purpose is to help new users draw attention to the many different issues that need to be considered when designing high-speed circuit PCB layout. Another purpose is to provide a refresher for customers who haven’t been exposed to PCB routing in a while.Due to limited space, this article cannot discuss all issues in detail, but we

Printed circuit board (PCB) routing plays a critical role in high-speed circuits, but it is often one of the last steps in the circuit design process. There are many aspects of high-speed PCB routing, and a great deal of literature has been written on the subject. This paper mainly discusses the wiring problems of high-speed circuits from a practical point of view. The main purpose is to help new users draw attention to the many different issues that need to be considered when designing high-speed circuit PCB layout. Another purpose is to provide a refresher for customers who haven’t been exposed to PCB routing in a while. Due to limited space, this article cannot cover all issues in detail, but we will discuss the key parts that have the greatest impact on improving circuit performance, reducing design time, and saving modification time.

Although the focus here is on circuits related to high-speed operational amplifiers, the issues and methods discussed here are generally applicable to the wiring used for most other high-speed analog circuits. When an op amp operates in the very high radio frequency (RF) frequency band, the performance of the circuit is largely determined by the PCB layout. A high-performance circuit design that looks good on the “drawing” will end up with mediocre performance if it is compromised by careless wiring. Anticipating and paying attention to important details throughout the routing process will help ensure expected circuit performance.

Schematic

Although a good schematic does not guarantee good routing, good routing starts with a good schematic. Be thoughtful when drawing the schematic, and you must consider the signal flow of the entire circuit. If you have normal steady signal flow from left to right in the schematic, you should have equally good signal flow on the PCB. Give as much useful information as possible on the schematic. Because sometimes the circuit design engineer is not available, the customer will ask us to help solve the problem of the circuit, and the designers, technicians and engineers who do this work will be very grateful, including us. In addition to the usual reference identifiers, power consumption, and error tolerance, what information should be given in the schematic? Here are some suggestions for turning an ordinary schematic into a first-class schematic. Add waveforms, mechanical information about the enclosure, trace lengths, blank areas; indicate which components need to be placed on the PCB; give adjustment information, component value ranges, heat dissipation information, controlled impedance traces, notes, brief circuit Action description… (and more).

don’t believe anyone

If you didn’t design the wiring yourself, be sure to allow plenty of time to double-check the wiring person’s design. A small prevention at this point is worth a hundred times the remedy. Don’t expect the wiring guy to understand what you’re thinking. Your input and guidance is paramount early in the cabling design process. The more information you can provide and the more involved you are throughout the routing process, the better the resulting PCB will be. Set a tentative completion point for the routing design engineer – a quick check against the routing progress report you want. This “closed loop” approach prevents routing from going astray, thereby minimizing the possibility of rework. Instructions to be given to the layout engineer include: a brief description of the circuit’s function, a schematic diagram of the PCB showing where the inputs and outputs are, PCB stack-up information (e.g. how thick the board is, how many layers there are, details of each signal layer and ground plane – functional loss, ground, analog, digital, and RF); which signals are required for each layer; where important components are required; exact locations of bypass components; which traces are important; which traces require controlled impedance traces ; which traces need to be matched in length; the size of the components; which traces need to be kept away (or close) to each other; which traces need to be kept away (or close) to each other; On the top of the PCB, which ones are placed on the bottom. Never complain that too much information needs to be given to others – too little? Yes; too much? No. A learning experience: About 10 years ago, I designed a multi-layer surface mount circuit board — the board has components on both sides.

The board is fastened to a gold-plated aluminum case with a lot of screws (because of the very strict anti-vibration specifications). The pins that provide the bias feedthrough go through the board. This pin is connected to the PCB by solder wire. This is a very complicated device. Some components on the board are for test setup (SAT). But I have clearly specified the location of these components. Can you guess where these components are mounted? By the way, under the board. Product engineers and technicians were unhappy when they had to take the whole unit apart, put it back together after setting it up. I haven’t made this mistake since.

Location

Just like in a PCB, location is everything. It’s all very important where to place a circuit on the PCB, where to mount its specific circuit components, and what other circuits are adjacent to it. Usually, the location of the input, output and power supply is predetermined, but the circuit between them needs to “play their own creativity”. That’s why paying attention to wiring details will pay off hugely. Start with the location of key components and consider the specific circuit and the entire PCB. Specifying the location of critical components and the routing of signals from the outset helps ensure that the design works as intended. Getting the design right the first time reduces cost and stress — and shortens development cycles.

Bypass power

Bypassing the power supply at the power supply side of an amplifier to reduce noise is an important aspect of the PCB design process — whether for high-speed op amps or other high-speed circuits. There are two common configuration methods for bypassing high-speed op amps. Power-Supply Ground: This method works best in most cases, using multiple capacitors in parallel to connect the op amp’s power pins directly to ground. Typically two parallel capacitors are sufficient – but adding parallel capacitors may be beneficial in some circuits. Capacitors of different values ​​in parallel help ensure that the power pins see only low alternating current (AC) impedance over a wide frequency band. This is especially important at op amp power supply rejection ratio (PSR) attenuation frequencies. This capacitor helps compensate for the reduced PSR of the amplifier. Maintaining a low-impedance ground path over many decades will help ensure that unwanted noise cannot enter the op amp. Figure 1 shows the advantage of using multiple capacitors in parallel. At low frequencies, large capacitors provide a low impedance path to ground. But once the frequency reaches their own resonant frequency, capacitors become less capacitive and gradually become inductive. This is why it is important to use multiple capacitors: when the frequency response of one capacitor starts to drop, the frequency response of the other capacitor starts to play its part, so the AC impedance can be kept very low over many octaves.

Figure 1. Capacitor impedance versus frequency.

Start directly with the op amp’s power pins; the capacitor with the smallest capacitance value and smallest physical size should be placed on the same side of the PCB as the op amp — and as close to the amplifier as possible. The ground terminal of the capacitor should be connected directly to the ground plane with the shortest possible lead or trace. The above ground connection should be as close as possible to the load side of the amplifier to reduce interference between the power supply and ground. Figure 2 shows this connection method.

Figure 2. Shunt capacitors bypassing supply terminals and ground.

This process should be repeated for the next largest capacitor value. It is best to start with a 0.01 μF minimum capacitance value and place a 2.2 μF (or larger) electrolytic capacitor close by with a low equivalent series resistance (ESR). A 0.01 μF capacitor in a 0508 case size has very low series inductance and excellent high frequency performance. Supply to Supply: Another configuration method uses one or more bypass capacitors connected across the positive and negative supply terminals of the op amp. This method is often used when it is difficult to configure four capacitors in a circuit. The disadvantage is that the capacitor’s case size may increase because the voltage across the capacitor is twice the value of the single-supply bypass method. Increasing the voltage requires increasing the rated breakdown voltage of the device, that is, increasing the case size. However, this approach can improve PSR and distortion performance. Because each circuit and wiring is different, the configuration, number, and capacitance value of capacitors must be determined according to the actual circuit requirements. Parasitics Parasitics are those glitches (literally) that slip into your PCB and wreak havoc in your circuit, causing headaches and unknown causes. They are the parasitic capacitances and parasitic inductances that permeate high-speed circuits. These include parasitic inductances due to package lead and trace lengths; parasitic capacitances from pad-to-ground, pad-to-power plane, and pad-to-trace; via interaction, and Many other possible parasitic effects. Figure 3(a) shows a typical non-inverting operational amplifier schematic. However, if parasitic effects are considered, the same circuit may become as shown in Figure 3(b).

Figure 3. Typical op amp circuit, (a) original design, (b) after considering parasitics.

In high-speed circuits, very small values ​​can affect the performance of the circuit. Sometimes tens of picofarads (pF) of capacitance is sufficient. A related example: If there is only 1 pF of additional parasitic capacitance at the inverting input, it can cause spikes of almost 2 dB in the frequency domain (see Figure 4). If the parasitic capacitance is large enough, it can cause circuit instability and oscillation.

Figure 4. Additional spikes caused by parasitic capacitance.

When looking for problematic parasitic sources, there may be several basic formulas for sizing those parasitic capacitances mentioned above. Equation (1) is the formula for calculating the parallel plate capacitor (see Figure 5).

(1) C represents the capacitance value, A represents the plate area in cm2, k represents the relative permittivity of the PCB material, and d represents the distance between the plates in cm.

Figure 5. Capacitance between two plates.

Ribbon inductance is another parasitic effect to consider, caused by long traces or lack of ground planes. Equation (2) shows the formula for calculating the trace inductance (Inductance). See Figure 6. ? ? ? jQuery183016061163768339437_1549938012633

(2) W represents the width of the printed line, L represents the length of the printed line, and H represents the thickness of the printed line. All dimensions are in mm.

Figure 6. Trace inductance.

The oscillation in Figure 7 shows the effect of a trace length of 2.54 cm at the non-inverting input of a high-speed op amp. Its equivalent parasitic inductance is 29 nH (10-9H), which is sufficient to cause sustained low-voltage oscillations that last throughout the transient response cycle. Figure 7 also shows how a ground plane can be used to reduce the effects of parasitic inductance.

Figure 7. Impulse responses with and without a ground plane. Vias are another source of parasitics; they can cause parasitic inductance and parasitic capacitance. Equation (3) is the formula for calculating the parasitic inductance (see Figure 8).

(3) T represents the thickness of the PCB, and d represents the diameter of the through hole in cm.

Figure 8. Through-hole dimensions.

Equation (4) shows how to calculate the value of parasitic capacitance due to vias (see Figure 8).

(4) εr represents the relative permeability of the PCB material. T represents the thickness of the PCB. D1 represents the diameter of the pad around the via. D2 represents the diameter of the isolation hole in the ground plane. All dimensions are in cm.

A single via in a 0.157 cm thick PCB can add 1.2 nH of parasitic inductance and 0.5 pF of parasitic capacitance; this is why it is important to be vigilant when routing the PCB to minimize the effects of parasitics minimum. Ground planes actually need to be discussed much more than this article, but we will highlight some key features and encourage readers to explore this topic further. The ground plane acts as a common reference voltage, provides shielding, can dissipate heat, and reduces parasitic inductance (but it also increases parasitic capacitance). While there are many benefits to using a ground plane, it must also be implemented with care as it has some limitations on what can and cannot be done. Ideally, one layer of the PCB should be dedicated as a ground plane. This produces the best results when the entire plane is not destroyed. Never misappropriate the area of ​​the ground plane in this dedicated layer for other signals. Since the ground plane cancels the magnetic field between the conductor and the ground plane, the trace inductance can be reduced. Disrupting an area of ​​the ground plane can introduce unexpected parasitic inductance to traces above or below the ground plane. Because ground planes typically have a large surface area and cross-sectional area, keep the resistance of the ground plane to a minimum. At low frequencies, the current will choose the path of least resistance, but at high frequencies, the current will choose the path of least impedance. There are exceptions, however, and sometimes a small ground plane is better. High-speed op amps work better if the ground plane is moved away from the input or output pads. Instability due to parasitic capacitance introduced at the ground plane at the input increases the input capacitance of the op amp and reduces the phase margin. As seen in the discussion of parasitics, a capacitance of 1 pF at the input of an op amp can cause significant spikes. Capacitive loads on the output—including parasitic capacitive loads—create poles in the feedback loop. This reduces the phase margin and causes the circuit to become unstable. If possible, analog and digital circuits — including their respective grounds and ground planes — should be separated. Fast rising edges can cause current glitches to flow into the ground plane. Noise caused by these fast current glitches can destroy analog performance. Analog and digital ground (and power) should be connected to a common ground to reduce circulating digital and analog ground currents and noise.

At high frequencies, a phenomenon called the “skin effect” must be considered. The skin effect causes current to flow to the outer surface of the wire—the result is a narrower cross-section of the wire, thus increasing the direct current (DC) resistance. While the skin effect is beyond the scope of this article, here is a good approximation (in cm) for the Skin Depth in copper wire:

(5) Low-sensitivity electroplating metal helps to reduce the skin effect. A wide variety of analog and digital signals exist on routing and shielding PCBs, ranging from high to low voltages or currents, from DC to GHz frequency ranges. It is very difficult to ensure that these signals do not interfere with each other. Recalling the advice in the “Trust no one” section above, it’s crucial to think ahead and make a plan for how to handle the signals on the PCB. It is important to note which signals are sensitive and to determine what must be done to ensure signal integrity. The ground plane provides a common reference point for electrical signals and can also be used for shielding. If signal isolation is required, physical distance should first be established between signal traces. Here are some practical lessons to learn from: Reducing the length of long parallel lines in the same PCB and the proximity of signal traces can reduce inductive coupling. Capacitive coupling can be prevented by reducing the length of long traces on adjacent layers. Signal traces that require high isolation should run on different layers and – if they cannot be completely isolated – should run orthogonal traces with a ground plane between them. Orthogonal routing minimizes capacitive coupling, and the ground wire forms an electrical shield. This method can be used when forming controlled impedance traces. High frequency (RF) signals typically flow on controlled impedance traces. That is, the trace maintains a characteristic impedance such as 50Ω (typical in RF applications). The two most common controlled impedance traces, microstrip line 4 and strip line 5, can achieve similar effects, but in different ways. A microstrip controlled impedance trace, shown in Figure 13, can be used on either side of the PCB; it uses the ground plane directly below it as its reference plane.

Figure 13. Microstrip transmission line. Equation (6) can be used to calculate the characteristic impedance of an FR4 board. ?

(6) H is the distance from the ground plane to the signal trace, W is the trace width, and T is the trace thickness; all dimensions are in mils (10-3 inches). εr represents the dielectric constant of the PCB material. Ribbon controlled impedance traces (see Figure 14) use two ground planes with signal traces sandwiched between them. This method uses more traces, requires more PCB layers, is sensitive to dielectric thickness variations, and is more expensive—so it is usually only used in demanding applications.

Figure 14. Ribbon controlled impedance trace. The characteristic impedance calculation formula for stripline is shown in formula (7).

(7) A guard ring, or “isolation ring”, is another shielding method commonly used in op amps to prevent parasitic currents from entering sensitive nodes. The basic principle is simple – the sensitive junction is completely surrounded by a guard wire that maintains or forces it to maintain (low impedance) the same potential as the sensitive junction, thus keeping the absorbed parasitic current away from the sensitive junction.

Figure 15(a) shows the schematic for guard rings in the op amp inverting and non-inverting configurations. Figure 15(b) shows typical routing methods for the two guard rings in the SOT-23-5 package. ??

Figure 15. Guard ring. (a) Inverting and non-inverting work. (b) SOT-23-5 package. There are many other shielding and wiring methods. For more information on this and other topics above, the reader is advised to read the following references. Conclusion A high level of PCB layout is important for successful op amp circuit design, especially for high speed circuits. A good schematic is the foundation of good wiring; close coordination between the circuit design engineer and the wiring design engineer is fundamental, especially regarding the placement of components and wiring. Issues to consider include bypassing power supplies, reducing parasitics, using ground planes, the impact of op amp packaging, and routing and shielding.

1. During PCB design, capacitors such as bypass filters at the chip power supply should be as close to the device as possible, and the typical distance is less than 3MM.

2. The small ceramic bypass capacitor at the power supply of the operational amplifier chip can provide energy for the high-frequency characteristics of the amplifier when the amplifier is inputting high-frequency signals. The choice of capacitance value is selected according to the frequency of the input signal and the speed of the amplifier. For example, a 400MHz amplifier Possible 0.01uF and 1nF capacitors installed in parallel.

3. When we buy capacitors and other devices, we also need to pay attention to their self-resonant frequency. Capacitors whose self-resonant frequency is around this frequency (400MHz) are useless.

4. When drawing the PCB, do not run other lines under the input and output signal pins of the amplifier and the feedback resistor, which can reduce the interaction of parasitic capacitances between different lines and make the amplifier more stable

5. The high-frequency performance of surface mount devices is better and the volume is small

6. When wiring the circuit board, keep the traces as short as possible and pay attention to their length and width to minimize parasitic effects

7. For the processing of the power line, the parasitic characteristics of the power line are the worst DC resistance and self-inductance, so we should widen the power line as much as possible.

8. The current on the input and output connection lines of the amplifier is very small, so they are easily affected by parasitic effects that are harmful to them.

9. For signal paths exceeding 1CM, it is best to use a transmission line with controlled impedance and termination (matching resistance) at both ends

10. Amplifier driving resistive-capacitive load In order to solve the problem of stability, a common technique is to introduce a resistor ROUT and preferably close to the op amp, so that the isolation of the capacitive load is achieved by using a series output resistor.

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