“With the rapid development of Electronic technology and computer technology, the technical means to carry out advanced aircraft power distribution system research in China is much better than that of foreign countries in the 1980s. The research on solid-state power control system is based on the current development of aircraft power distribution system. Originally, the single-switch structure is currently on the market. Recently, the multi-switch SSPC group has been under research and development. The SSPC group shares a large-scale control chip, which can further improve power density and expand functions. At present, the foreign companies that conduct research include India and Liqi in the United States, and the domestic research is in the stage of engineering prototypes.
Author: innovation point
With the rapid development of electronic technology and computer technology, the technical means to carry out advanced aircraft power distribution system research in China is much better than that of foreign countries in the 1980s. The research on solid-state power control system is based on the current development of aircraft power distribution system. Originally, the single-switch structure is currently on the market. Recently, the multi-switch SSPC group has been under research and development. The SSPC group shares a large-scale control chip, which can further improve power density and expand functions. At present, the foreign companies that conduct research include India and Liqi in the United States, and the domestic research is in the stage of engineering prototypes.
2. Block diagram of the overall structure of the system
3. Hardware Design
3.1 Logic control device
According to the design requirements, it is necessary to integrate multiple SSPCs on one circuit board. If the digital circuit is completely implemented with separate components, the volume of the digital circuit is quite large, so we use a complex programmable logic device-CPLD. ALTERA’s programmable logic devices are the fastest and largest in the industry. The company’s PLD devices not only have the general advantages of PLDs, but also have the following advantages: high performance, high integration, reasonable price, and short development cycles and good for programming.
According to the resources required by the software, the logic master chip adopts the EPM3256ATC144-10 in the MAX3000A series chip of ALTERA Company. Compared with the MAX7000 series, the I/O voltage of the MAX3000A series is +3.3V, while the I/O voltage of the MAX7000 series is +5V, in general, for the output of control signals, the +5V voltage is more reliable, but low voltage and low power consumption are the future development trends, and it is also conducive to the design of future replacement products, and the consideration of reliability The requirements of system design can be achieved by strengthening the design of peripheral circuits.
3.2 Driving circuit of power MOSFET
After the control command is isolated and output by the optocoupler, it is connected to the non-inverting input terminal of the comparator LM311, and the inverting input terminal of the comparator inputs the reference level Vref, which takes Vref=3V. When DRV_SSPC1=1, the optocoupler outputs a high level, the voltage at the non-inverting input terminal of the comparator is greater than the voltage at the inverting input terminal, and the comparator output DRC_OUT is a high level: when DRV_SSPC1=0, the optocoupler outputs a low level, comparing The voltage of the non-inverting input terminal of the comparator is less than the voltage of the inverting input terminal, the comparator output DRC_OUT is low level; the output terminal of the comparator is connected to the low-value resistor R30, the purpose is to form a certain time with the parasitic capacitance between the G pole and the D pole of the power MOSFET The resistance-capacitance delay of the MOSFET ensures that the conduction time of the MOS tube is not too fast or too slow, and reduces parasitic oscillation. The resistance value should decrease with the increase of the rated current value of the driven device.
3.3 Signal acquisition circuit
1. Analog acquisition circuit. Signal sampling! The block diagram of conditioning is shown in Figure 3. The analog signal passes through the isolation circuit to obtain the sampling voltage, and after a certain proportion of amplification, impedance matching is carried out through the follower, and finally, after filtering, the AC component in the signal is filtered out, and the obtained signal can be sent to the analog of the A/D converter. input.
The analog voltage signal that needs analog-to-digital conversion is a DC voltage signal, and the range is about 0V-7V. Since SSPC is used as a switch protection measure for the load in the circuit, it is required that its action time is as fast as possible, and the precision is small. To each link of the circuit, the conversion time of the A/D converter is required to be as small as possible, and a compromise solution is obtained by weighing the conversion accuracy and conversion time of the A/D. After comparison, AD7874, a 12-bit A/D converter from AD Company, is used, which is a 4-channel simultaneous sampling, 12-bit fast and low-power A/D converter, which includes a 12-bit high-speed analog-to-digital converter, On-chip clock and four sample/holds. This avoids the problem of four input channels sharing a sample/hold – a phase difference between the samples.
2. Switch value acquisition circuit. There are two main switching quantities: STA_LOAD, which represents the load state, and STA_SSPC, which represents the state of the power MOSFET. Regulation: When the load current is greater than 15% of the rated current of the SSPC, the switch value STA_LOAD indicating the load state is low (0); when the MOSFET is in the on state, the switch value STA_SSPC=1 indicating the on-off state of the MOSFET. Judging by the data of the A/D channel collected by the CPLD: when i_load is greater than 15% of the load current, it indicates that the load is turned on, and STA_LOAD0 is set; when i_load is less than 15% of the load current, it indicates that the load does not work, and STA_LOAD is set is 1. STA_LOAD is output through the I/O port of the CPLD.
3. I/O drive and isolation circuit design. When the CPLD interfaces with peripheral devices, the drive capability should be considered, and drivers and isolation devices should be added in the middle to protect the CPLD from damage. Because the comparator is powered by 12V, the output status signal is a 12V signal, and the CPLD of the logic judgment module is powered by 3.3VI/O and 2.5V core, so the collection of SSPC status signals and the output of control signals need to go through Level conversion and electrical isolation, specifically using optocoupler isolation, not only achieves electrical isolation, but also achieves level conversion. When the control signal is output from the CPLD, the drive current of the optocoupler is relatively large (about 20mA). If it is driven directly from the CPLD output, the CPLD cannot be driven because the current is too small. The device 74HC04 is used to drive the previous stage of the optocoupler. As for the signal input to the CPLD, because it is output from the optocoupler, the current is generally not large (Ic Inverter.
3.4 Power circuit
4. Programmable logic area design
1. A/D data acquisition module. Using the concept of a state machine, a step corresponds to a state, and each state is assigned a specific function to the CPLD. The work of AD7874 is roughly divided into 10 step intervals. The quantization noise converted by AD7874 is related to the number of output bits and the quantization step size. The more output bits and the smaller the quantization step size, the smaller the quantization noise. The actual A/D converter is mostly fixed-point system, the dynamic range is ±1, and the maximum output value is 1.If only quantization noise is considered, the signal-to-noise ratio of the input signal is
If the AD7874 is 12 bits, the SNR=70dB, which is generally enough in the application, and the word length is not very necessary because the input analog signal itself has a certain signal-to-noise ratio. It doesn’t make sense for the signal to have a lower noise level.
2. Switch quantity acquisition module. Due to the existence of various interferences in the control signal downloaded by the host computer, the switching value often appears jitter in the experiment. On the other hand, the switching value (such as STA_SSPC) obtained by the comparator in the circuit is Stable, occasional current overshoot will make the switch signal sent to the CPLD also jitter; these will cause the SSPC to frequently malfunction. For this reason, a special switch de-jitter circuit needs to be designed to reduce the probability of SSPC malfunction. In practice, the rear stage of the delay circuit plus the RS flip-flop is used. The specific working principle is as follows: firstly, the input signal is first led to the input terminal, after the two-stage D flip-flop delay, and then the RS flip-flop is used to make the signal. deal with.
3. The whole data analysis process includes the following parts:
(1) When the current is within the rated range, the SSPC works normally;
(2) When the current is greater than the rated voltage and less than 800% of the rated voltage, the SSPC enters the inverse time protection;
(3) When the current is greater than 800% of the rated current, the SSPC will trip immediately.
4. Logical judgment module. The logic judgment module will comprehensively obtain the on/off command of the power MOSFET after the collected current signal, the received control command and the internal state after logical judgment, as the input signal of the drive circuit. The program flow is shown in Figure 5. In the control of SSPC, the most likely problem is malfunction. For this reason, a more complex control logic is adopted to reduce the probability of SSPC malfunction. The control of SSPC is accomplished through two steps of “adjacent two bits and multiple instructions”. Only when several conditions are satisfied at the same time can the SSPC act. One is indispensable, which greatly reduces the probability of SSPC malfunction.
The author’s innovation
In this paper, the research and design of DC solid-state power control system based on CPLD control. Completed the SSPC peripheral hardware circuit design, including the connection of the main control chip and the A/D conversion chip MOSFET main circuit and buffer protection circuit, analog acquisition circuit, switch acquisition circuit, power supply circuit, etc.; completed the programmable logic part on CPLD The implementation of VHDL, including A/D converter control, current segmental protection, SSPC action command judgment logic generation, etc.
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