“For applications that require high dynamic range, sigma-delta converters are often used. These applications can mainly be found in the fields of chemical analysis, healthcare and weight management. However, many of these modules cannot be converted quickly. The circuit in Figure 1 describes a method for combining high dynamic range with high slew rate.
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Author: Thomas Tzscheetzsch
problem:
Can a 16-bit SAR converter application achieve a dynamic range of 125 dB at 600 kSPS?
Answer:
Yes, 89 dB + 18 dB + 20 dB ≥ 125 dB.
Introduction
For applications that require high dynamic range, sigma-delta converters are often used. These applications can mainly be found in the fields of chemical analysis, healthcare and weight management. However, many of these modules cannot be converted quickly. The circuit in Figure 1 describes a method for combining high dynamic range with high slew rate.
The circuit in Figure 1 shows a 16-bit SAR converter with 2.5 MSPS and an upstream programmable instrumentation amplifier that sets the gain to 1 or 100. With oversampling and digital signal processing in the FPGA, the circuit achieves a dynamic range greater than 125 dB and is still very quiet. The high dynamic range is achieved by the AD8253’s automatic switching and oversampling, where the signal is sampled at a rate well above the Nyquist frequency. As a rule of thumb, doubling the sampling frequency improves the signal-to-noise ratio (SNR) by about 3 dB at the original signal bandwidth. In the circuit shown in Figure 1, digital filtering is still applied in the FPGA to remove noise above the signal bandwidth of interest. The principle is shown in Figure 2.
Figure 1. SAR converter with automatic gain adjustment.
For maximum dynamic range, use an instrumentation amplifier at the input to amplify very low signals by a factor of 100. Some notes about noise are as follows:
For a dynamic range requirement of >126 dB, the maximum noise level generated is 1 µV rms at a 3 V (6 V pp) input signal. The AD7985 is a 16-bit SAR converter with 2.5 MSPS. If it runs at 600 kSPS (11 mW for low power loss) and an oversampling factor of 72, that yields a sampling rate of about 8 kSPS, so the bandwidth is 4 kHz. Under these conditions, a maximum noise density (ND) of 15.8 nV/√Hz will result. This value is important for selecting the correct instrumentation amplifier. The ADC typically has an SNR of 89 dB, and oversampling by a factor of 72 adds an additional 18 dB, so it still takes about 20 dB to hit the 126 dB target, which is the job of the instrumentation amplifier. When the AD8253 has a gain of 100, its value is 11 nV/√Hz. The AD8021 below, used as an ADC driver and used for leveling, adds another 2.1 nV/√Hz of noise.
Figure 2. The increase in oversampling removes some of the noise.
The analog signal chain is completed by the reference ADR439 (or REF194) and the ADA4004-2 as the reference buffer and driver for generating the offset voltage.
In addition to the components in the analog path, the FPGA (or processor) is also important to circuit performance. The key task is to switch the gain of the instrumentation amplifier from 1 to 100. To this end, a number of thresholds are programmed to ensure that the ADC does not saturate. Therefore, the AD8253 operates at a gain of 100 for input voltages up to around 20 mV, which allows a maximum voltage of 2.0 V at the ADC input. The FPGA then reduces the AD8253’s gain to 1 with no delay to prevent overload (see Figure 3).
Figure 3. Example of a gain switch.
Variations of the circuit can be operated with other ADCs such as the AD7980 (16-bit, 1 MSPS), AD7982 (18-bit, 1 MSPS), or AD7986 (18-bit, 2 MSPS). Likewise, instead of using the AD8253 with gains of 1, 10, 100, and 1000, use instrumentation amplifiers such as the AD8251 with lower ranges (gains of 1, 2, 4, and 8). The choice of reference voltage may also change.
The complete development system can be found at analog.com/CN0260.
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Thomas Tzscheetzsch [[email protected] "For applications that require high dynamic range, sigma-delta convert…
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