LCD Display Inverter

Display Inverter / VGA Board / LCD Controller

Single-Ended-to-Differential Conversion Using AD8138 Low Distortion Differential ADC Driver and AD7356 5 mSpS, 12-Bit SAR ADC

This circuit can perform single-ended to differential conversion of the input signal of the 5 MSPS, 12-bit SAR ADC AD7356. This circuit provides sufficient settling time and low impedance to ensure peak performance from the AD7356. The ideal way to drive the AD7356 differentially is to use a differential amplifier such as the AD8138. The device can be used as a single-ended-to-differential amplifier or a differential-to-differential amplifier. The AD8138 also provides common-mode level shifting. To view this circuit note, visit:www.analog.com/en/CN-0041.

Buffers Enhance Clock Integrity, Help High-Performance, High-Speed ​​ADCs Achieve Specified Performance

Designers rely on high-performance, high-speed analog-to-digital converters (ADCs) to enable high-speed, high-precision, and high-resolution systems. One of the main criteria for selecting an ADC is the signal-to-noise ratio (SNR). Auxiliary design elements can affect the performance of the converter, and an important consideration is clock integrity. Jitter on the ADC input clock can degrade signal-to-noise performance, so maintaining a good low-noise, low-jitter clock signal throughout the system clock tree is a real challenge.

solution

Analog Devices has a wide variety of clock buffers designed to help designers address clock integrity challenges. Inserting the clock buffer between the converter and the system clock tree, the LVPECL fanout buffer easily achieves jitter performance of the order of 75 fs with extremely low skew, around 9 ps. These buffer ICs also provide up to 12 channels of low-jitter clock fanout and can steepen clock signal edges that are flattened by long traces on the PCB.

The ideal clock signal for a data converter should not only have low phase noise and low jitter, but also have very steep rising and falling edges.If only one or two converters require very steep edges, place the clock bufferADCLK905,ADCLK907, ADCLK914 and ADCLK925 Being next to the converter provides extremely fast edges with minimal impact on clock signal noise. In addition to providing steep edges, devices such as the ADCLK914 provide high differential voltage swings that limit ADC-coupled noise.

Analog Devices offers a variety of low-jitter clock buffer products from 1 to 12 outputs in different logic families to meet the clocking requirements of high-performance, high-speed ADCs.

The Links:   LTM170ET01 ITSX98E