LCD Display Inverter

The SFF SDR (Small Form Factor Software Defined Radio) development platform is a modular RF/IF/baseband platform (Figures 1 and 2). The platform showcases the latest silicon offerings from Xilinx and Texas Instruments (TI) as well as the latest advanced design flows and software architectures.The platform also provides specific key features for handheld device developers, such asreal-time power consumptionconfigureandsuperviseMeasurement.

Figure 1 – Module Platform of the SFF SDR Development Platform

The platform is the result of a joint development by Texas Instruments, Xilinx and Lyrtech, as well as a number of major software tool vendors. This platform features a Xilinx® Virtex-4 device whose advanced features enable you to develop efficient power-optimized designs.

This article will discuss the trend of combining DSP/FPGA architecture and design and how it is manifested in the SFF SDR development platform. This article will also describe a simple Home Radio Service (FRS) FM modulation method and a more complex GSM modulation method designed using a hybrid design flow (model-Based Development for FPGA and C/Assembly for System-on-Chip DSP).

Figure 2 – Block Diagram and Technology of the SFF SDR Development Platform

SFF SDR Development Platform

The SFF SDR development platform provides the complete signal chain from antenna to baseband processing. The system can be used to create single- or multi-protocol radio handsets for military, police and commercial applications. The system can also be used as a rapid prototyping and testing platform. Additionally, the platform is integrated for use with The MathWorks’ Simulink Model-Based Design (MBD) tool, so you can choose to use C/HDL or MATLAB Simulink to quickly test proof-of-concept designs and optimize the architecture for cost and power.

Unlike other SDR development products on the market, the SDR development platform is a software-hardware co-development environment that provides a complete set of components for multi-protocol SDR equipment, including RF front-end modules, analog-to-digital and digital-to-analog data conversion modules, and digital processing modules. By splitting baseband, IF, and RF into discrete modules rather than a single hybrid architecture, you can enhance your radio development capabilities by replacing your own or third-party modules, and optimize cost and power consumption. This flexibility is critical because it gives you the ability to adapt your product to changing industry requirements.

The baseband module features a Xilinx Virtex-4 SX35 FPGA and a TI TMS320DM6446 chip. The TI chip contains a TMS320CC64x+ DSP core and an ARM9 general purpose processor core. The SDR development platform has a unique power consumption measurement API. This API measures FPGA, DSP, and ARM loading and reports real-time power consumption data. This allows you to extract important information such as burst and peak power consumption at a specific data rate to accurately estimate battery life. You can also quickly estimate the power consumption impact of different system configurations. For example, you can try different allocations of system functions between the FPGA and DSP to get the best power/performance balance.

FRS and GSM application examples

The SFF SDR development platform includes a basic application example: a simple FRS FM waveform. The example shown in Figure 3 was designed entirely using a model-based approach to demonstrate the platform’s rapid prototyping capabilities. This application also shows how to distribute application functions between the DSP and FPGA, and shows the effect of “moving” different parts of the processing from the FPGA to the DSP (and vice versa).

(a) (b)
Figure 3 – Designing a simple FRS waveform using a “full model-based design” approach. Figure 3(a) shows DSP processing (Tx side); Figure 3(b) shows FPGA processing (Rx and Tx side).

Figure 4 shows the FPGA portion of the GSM physical layer implemented using the model-based approach in Simulink/Xilinx System Generator for DSP. This model is actually an executable block diagram in which all signal processing functions can be simulated and verified by combining Simulink signal sources, channel simulation, output oscilloscope, and data error rate analysis.

The advantage of this approach is that once the simulation is complete, the model can be synthesized into the FPGA bitstream for execution with the actual signal.

We first briefly explain the development process, and then go into a more in-depth discussion of very specific DSP-related implementation and timing implementation.

The original target device for this GSM project was the Virtex-II family, and the same System Generator block was resynthesized and reverified with a Virtex-4 device. It can be seen that the main benefit of using a model-based approach is to facilitate device redirection.

Figure 4 – FPGA model of GSM physical layer

The implementation of this redirection can pass the first pass, however, the use of the more advanced capabilities of the DSP48 processing unit in the Virtex-4 FPGA is to optimize the design, because the more optimized the design, the lower the power consumption. Figure 5 shows a key high-speed component of the model, the transmit-side IF mixer, running at the IF acquisition speed (104 MHz). Optimizing this part is the key to reducing power consumption. This is accomplished by “tuning” the DSP48 microcode (shown in the GUI subwindow), which is programmed to execute a multiply-add instruction. In this way, FPGA resources are much lower compared to Virtex-II devices. As a result of this optimization, power usage (verified with the platform’s power measurement function) will also be much lower, and the overall power profile of the Virtex-4 device will be improved.

Figure 5 also shows another very interesting optimization feature of System Generator, the retiming feature. This powerful feature allows System Generator to insert latches at appropriate locations throughout the pipeline. This automatic retiming feature does simplify things, especially for high-speed parts such as direct digital synthesis (DDS) functions.

The use of the Virtex-4 architecture and tools greatly benefits the implementation of the GSM physical layer. In terms of FPGA resources and power consumption, we have greatly optimized the implementation with the SFF’s power measurement capabilities. Additional features, such as continuous power monitoring, will allow you to characterize power usage during operations, allowing for further processing optimization.

Figure 5 – Customizing the DSP48 Processing Unit with Microcode

in conclusion

The SFF SDR development platform provides a very flexible platform for handheld device developers. Backed by advanced processors from chip suppliers such as TI and Xilinx, and software tools from major suppliers such as The MathWorks, this platform provides handheld developers with a true “Lego box” that is accelerating, competing Advanced products are built in the intense and promising wireless device market.