# LCD Display Inverter

Display Inverter / VGA Board / LCD Controller

## Stable Range of Equivalent Series Resistance of LDO Regulators

This article investigates the stable range of equivalent series resistance (ESR) values ​​for LDO regulators. Discuss LDO frequency response with LDO regulator ac mode. Examine stable and unstable ESR ranges.

This article investigates the stable range of equivalent series resistance (ESR) values ​​for LDO regulators. Discuss LDO frequency response with LDO regulator ac mode. Examine stable and unstable ESR ranges. LDO regulator ac mode

Figure 1 shows the main components of a PMOS LDO regulator. The LDO regulator can be divided into 4 separate functional blocks: pass element, reference, sampling resistor and error amplifier. The error amplifier is modeled with a transconductance ga loaded with capacitor Cpar and resistor Rpar. The parasitics (Cpar, Rpar) represent the output impedance of the error amplifier and the input impedance of the series pass element. The series pass element (PMOS transistor) is modeled with the transconductance gp small signal mode. Add an output capacitor Co (equivalent series resistance RESR) and bypass capacitor Cb. The output impedance can be obtained from Figure 1:

Zo=R12P‖（RESR+1 / SCo）‖1 / SCo (1)

=R12p(1+SRESRCo) / S2R12pRESRCb+S[(R12p+RESR)Co+R12pCb]+1

in the formula

R12p=Rds‖(R1+R2)≈Rds (2)

Typically, the output capacitor value Co is much larger than the bypass capacitor Cb. Therefore, the output impedance Zo is approximately expressed as:

Zo≈Rds(1+SRESRCo) / [1+S(Rds+RESR)Co]+[1+S(Rds‖RESR)Cb] (3) From equation (3), a portion of the total open-loop transfer function of the regulator is obtained, and the zeros and poles are obtained. The first pole is:

Po; S(Rds+RESR)Co=-1 (4)

so

fpo=-1 / 2π(Rds+RESR)Co≈-1 / 2πRdsCo (because R≥RESR) (5)

Find the 2nd pole from Equation 3:

Pb; S(Rds‖RESR)Cb=-1 (6) so

fpb=-1 / 2π(Rds‖RESRCb)≈-1 / 2πRESRCb (7)

Zero is:

ZESR; SRESR Co=-1 (8)

So fz(ESR)=-1 / 2πRESRCo (9) In addition, there is another pole through the component input impedance (ie amplifier output impedance Rpar, CPAR). The approximate poles and zeros of the LDO regulator are given by: Po≈1 / 2πRdsCo≈IL / 2πVACo (10)

Pb≈1 / 2πRESRCb (11)

Pa≈1/2πRparCpar(12)

ZESR≈1 / 2πRESRCo (13)

In the formula: RDs≈VA/IL, VA=1/λ (MOS device), and λ is the channel length modulation parameter. The pole Pa is only used at the input through the device, not at the output of the device. From the obtained poles and zeros, a typical frequency response of an LDO regulator is obtained, see Figure 2. The pole Po depends on the load current. At low load currents, the pole response occurs at a considerably lower frequency, thus reducing the phase margin. Worst stability occurs at ESR limits and low load currents. ESR Stability Range

LDO regulators require an output capacitor (with an output equivalent series resistor) to stabilize the control loop. As shown in Figure 3, if not compensated, the LDO has two poles that cause instability. Obviously, the linear regulator is unstable because at 1 gain frequency (UGF) the phase shift is -180° (ie phase margin = 0°), which is due to the two poles (Po, Pa) at low frequencies caused by the impact. To stabilize the regulator, a zero must be added, which will remove the phase effect of one of the two poles.

The output capacitor ESR or Compensating Series Resistor (CSR) is used for the zero point. Figure 4 shows how the ESR (or CSR) zero stabilizes the control loop. The zero created by the ESR is positioned before the UGF so that the phase margin at UGF1 will be greater than 0°. Therefore, the linear regulator becomes stable. For the stability of the system, the phase tolerance of the control loop at UGF should be greater than 0°.

The ESR value should be kept within the range that determines the stability of the loop. In most cases, LDO regulators have minimum/maximum ESR values. As can be seen from equations 11 and 13, ESR determines the zero Zesr and the pole Pb. When ESR changes, Zesr and Pb drift up/down, affecting loop stability. Figure 5 shows the frequency response of the LDO instability when the ESR is too large, and Figure 6 shows the frequency response of the LDO instability when the ESR is too small. In both cases the phase margin at UGF is less than or equal to 0°, resulting in system instability. Figures 5 and 6 show the stable range of Zers.

Since ESR can lead to instability, LDO manufacturers typically provide a graph representing the stable range of ESR values. Figure 7 shows a typical range of ESR values ​​versus output current (TPS76933 3.3VLDO regulator). This curve is called the “Tunnel of Death”. This curve shows that the ESR must be between 0.1Ω and 8Ω. Tantalum electrolytic, aluminum electrolytic and multilayer ceramic capacitors all meet ESR requirements.

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