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TSMC’s 3nm mass production is imminent, announcing that Synopsys’ digital and custom design platform has been certified

Synopsys, an IC designer, is committed to optimizing power, performance and area (PPA) for next-generation system-on-chips (SoCs), and announced that its digital and custom design platform has been certified by TSMC for its 3nm process. TSMC’s latest 3nm process technology is planned to be mass-produced in 2022.

Synopsys pointed out that the certification has passed strict verification and is based on TSMC’s latest design rule manual (DRM) and process design kit (PDK). Obtaining the certification can also be said to be the result of years of cooperation between the two parties. In addition, it has also obtained TSMC N4 process certification.

Suk Lee, deputy general manager of TSMC’s Design and Construction Management Office, said. Through the strategic cooperation between the two parties, TSMC enables customers to realize next-generation HPC, mobile, 5G and AI designs and bring innovative products to market quickly. Additionally, the digital design flow is based on the tightly integrated Synopsys Converged Design Platform, using the latest technologies to ensure faster timing closure, from synthesis to place and route to timing and physical signoff The correlation between the complete process. The platform’s enhanced synthesis and global placer Security C-TSMC Secret (global placer) engine can optimize library cell selection and placement results.

Synopsys emphasized that in order to support TSMC’s ultra-low voltage design convergence, the Synopsys optimization engine has been changed to use a new footprint optimization algorithm. These new technologies based on the strategic partnership between the two parties will help improve the PPA of TSMC’s N3 process design. The CustomCompiler design and layout solution, part of the Synopsys Custom Design Platform, brings greater productivity to designers using TSMC’s advanced manufacturing technologies.

A number of CustomCompiler enhancements have been certified by early 3nm users such as Synopsys’ DesignWare IP team, which can reduce the effort required for 3nm technology. Synopsys PrimeSim HSPICE, PrimeSim SPICE, PrimeSim Pro, and PrimeSim XA simulators are part of PrimeSim’s continuous solution, improving turnaround time for TSMC 3nm chip designs and providing signoff for circuit simulation and reliability requirements Category (signoff coverage).

Shankar Krishnamoorthy, general manager of Synopsys’ Digital Design Group, said that the ongoing partnership between Synopsys and TSMC brings highly differentiated solutions to advanced 3nm processes, giving customers greater confidence in their success when designing complex SoCs. In the overall process, designers are able to take full advantage of the advancements in PPA for next-generation HPC, mobile, 5G and AI designs thanks to a number of technological innovations that enable the 3nm process.