LCD Display Inverter

Display Inverter / VGA Board / LCD Controller

Use MIG to expand memory on Zynq (2)-Vivado articles

Hardware platform: ZC706 development board

Software tool: Vivado 2013.2

Step 1: Create a project

Start Vivado 2013.2 and create a new project zc706_mig. Select Create project subdirectory.

Choose RTL Project

Next, select the ZC706 development board on the Default Part page.

Step 2: Configure Zynq

In the Flow Navigator window on the left, click Create Block Design, and fill in zynq for the Design Name.

Add the IP’ZYNQ7 Processing System’ in the Diagram Tab page.

Double-click processing_system7_1 to open the configuration interface. Cancel all peripherals and only keep the UART. UART1Use MIO 48..49. Turn off the output of FCLK_CLK0.

Step 3: Configure MIG

Add the IP’MIG 7 Series’ in the Diagram Tab page. Double-click mig_7series_1 to open the configuration interface.

On the Memory Selection page, select DDR3

In Controller Options, configure Clock Period to 1250ps, configure Memory Type=SODIMMS; Memory Part=MT8JTF12864HZ-1G6.

On the AXI Parameter page, configure Data Width=32 and ID width=12.

On the Memory Options page, configure Input Clock Period=5000ps(200MHz).

On the FPGA Options page, configure System Clock=Differential, Reference Clock=Use System Clock, and System Reset Polarity=ACTIVE HIGH.

On the Extended FPGA Options page, select DCI Cascade.

On the IO Planning Options page, select Fixed Pin Out, then import labfileszc706_mig_pinout.ucf, click Validate, ignoreSlightly warnings, click Next.

On the System Signals Selection page, click Next.

On the Summary page, click Next.

On the Simulation Options page, select Accept and click Next.

On the PCB Information page, click Next.

On the Design Notes page, click Generate.

Step 4: Establish a connection between IP

On the Diagram Tab page, click Run Connection Automation in the upper part of the window, select /mig_7series_1/S_AXI, the system will automatically add IP and establish a partial connection.

Click Run Connection Automation in the upper part of the window and select /mig_7series_1/sys_rst.

Connect /mig_7series_1/ui_clk to processing_system7_1/M_AXI_GP0_ACLK

Connect /mig_7series_1/aresetn to /proc_sys_rest/peripheral_aresetn[0:0]

Click Run Block Automation in the upper part of the window, select processing_system7_1

Click the plus sign in front of /mig_7series_1/SYS_CLK to expand this interface.

Select /mig_7series_1/sys_clk_p, right-click, and select Create Port. In the pop-up window, change the Type to Clock and fill in Frequency (MHz) as 200.

Do the same for /mig_7series_1/sys_clk_n.

Select the /mig_7series_1/DDR3 interface, right-click, and select Make External

Click the Regenerate Layout button at the bottom left of the Diagram Tab page, and the tool will automatically re-arrange. The generated results are as follows. Does it feel very beautiful?

Step 5: create constraints

Name it system and copy the following content to the constraint file:

set_property LOC G9 [ get_ports sys_clk_n]

set_property IOSTANDARD DIFF_SSTL15 [ get_ports sys_clk_n]

set_property LOC H9 [ get_ports sys_clk_p]

set_property IOSTANDARD DIFF_SSTL15 [ get_ports sys_clk_p]

set_property LOC A8 [ get_ports reset]

set_property IOSTANDARD LVCMOS15 [ get_ports reset]

# additional constraints

#

create_clock -name sys_clk_pin -period “5.0” [get_ports “sys_clk_p”]

Step 7: Design verification

In the Block Design window, right-click on zynq.bd, select Generate Output Products, then right-click, and select Create HDL Wrapper.

In the Flow Navigator window on the left, click Generate Bitstream.

On my computer, the bit file was generated after about 20 minutes.

Then in Vivado, click File->Export->Export Hardware for SDK and select Launch SDK.

In the SDK, you can use the template “Memory Tests” to create a project, and test to confirm that MIG is working properly.

Based on this, developers can flexibly adjust the working frequency of MIG’s AXI port and Memory port to complete the embedding that fits their own applications.Built-in design.

The Links:   LTM10C042 G270ZAN012 6MBI25J-120