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Using SiC FETs in Data Center Power Supplies and Telecom Rectifiers

We can foresee a massive wave of buildouts around the world with the deployment of 5G networks and will require many high-quality telecom rectifiers to provide the required power. To meet the need to improve efficiency, reduce operating costs, and reduce bill of materials costs, there is a renewed interest in wide-bandgap solutions. Likewise, there is an ongoing effort to upgrade server power supplies to achieve ever-increasing levels of energy efficiency while minimizing heat loss.Today, hyperscale data centers powering the digital economy, big data, IoT and artificial intelligence use 30KW+ server racks and highly sophisticated cooling

We can foresee a massive wave of buildouts around the world with the deployment of 5G networks and will require many high-quality telecom rectifiers to provide the required power. To meet the need to improve efficiency, reduce operating costs, and reduce bill of materials costs, there is a renewed interest in wide-bandgap solutions. Likewise, there is an ongoing effort to upgrade server power supplies to achieve ever-increasing levels of energy efficiency while minimizing heat loss. Today, hyperscale data centers powering the digital economy, big data, IoT, and artificial intelligence operate with server racks in excess of 30KW and highly sophisticated cooling management systems.

5G networks with larger antenna arrays (up to 64 transmit/64 receive), 100-1000x higher data rates, and serving the trillions of devices that make up the Internet of Things seem to require more power. Many technological improvements have been made to reduce the power required by each base station, but more base stations may be required. To provide advanced power management methods, the power supplies of these base stations must meet increasingly stringent efficiency requirements, from standby to full load.

New products of SiC FETs can achieve previously unattainable efficiency targets, and we will examine the main topologies and device capabilities in this article. We’ll discuss what we’re likely to learn in this area, where silicon-based superjunctions, SiC FETs, and gallium nitride (GaN) FETs are all competing.

some basics

Common to these supplies is a Power Factor Correction (PFC) section that rectifies AC to DC at near unity power factor with an output voltage of 400V, followed by a DC converter that converts 400V to 48V or 12V, for use within the system. Other point-of-load converters then power the CPU and the repository.

If you examine data center server power usage, it’s clear that most of its lifespan is spent on light to moderate loads. Therefore, the PFC stage and the DC-DC stage must have high efficiency under all load conditions, while also meeting the thermal constraints of peak load operation. The well-known 80 Plus standard for computing power can demonstrate this, as shown in Figure 1. Servers must meet Titanium standards and remain efficient even at 10% load. Figure 2 shows a typical specification for the Open Compute Project, which requires more than the titanium standard for 3.3KW-class power supplies.

Figure 1: The 80 Plus standard showing the calculation of power efficiency goals

Figure 2: 3.3KW server power supply specification from Open Compute Project

Figure 3 shows a typical power supply architecture including input bridge rectifier, simple dual interleaved boost converter (PFC) with 650V FET and SiC Junction Barrier Schottky (JBS) diode, and full bridge LLC stage DC converter. The input EMI filter is not shown in the figure. Typical switching frequencies used in the PFC stage are 65-150kHz. Here, power density needs to be compromised to achieve higher efficiency at lower frequencies, since switching at 150kHz instead of 30kHz allows the Inductor to be much smaller. This leads to the need to use silicon-based superjunction MOSFETs with SiC JBS diodes to maintain high efficiency while hard switching at 65-150kHz. Highly advanced superjunction MOSFETs can switch quickly, and SiC Schottky diodes help minimize MOSFET turn-on losses.

Figure 3: Common power supply configurations.After the input bridge rectifier, an interleaved PFC stage and a full-bridge LLC stage

At the LLC stage of the circuit, 650V MOSFETs are also typically used. The circuit maintains zero voltage switching (ZVS) operation and reduces turn-off current, so losses are much lower and allow operation at higher frequencies of 100-500kHz, resulting in a smaller transformer. On the secondary side, a very low on-resistance 80-150V silicon MOSFET is used to rectify the high frequency secondary AC voltage to provide a stable DC output voltage. The 650V FET was chosen so that the recovery of the parasitic diode would not be disruptive when ZVS is lost under certain operating conditions.

semiconductor device

Looking at the transistors again, 650V-class devices are usually used in the PFC stage and the high-voltage side of the DC converter. Table 1 provides an overview of the state-of-the-art in silicon, GaN, and SiC devices and their associated properties. In terms of resistance per unit area (RdsA) affecting chip size, SiC FETs (RdsA for SiC JFETs) are by far the best choice. All wide-bandgap devices have excellent parasitic diode recovery performance compared to silicon-based superjunction alternatives. However, only SiC devices and silicon devices can handle avalanche energy. Threshold voltage of enhancement mode GaN devices (Vth) is also low, which, combined with its speed and narrow gate voltage range, makes it difficult to drive.

Table 1: Basic technical comparison of 650V transistor options

Table 2 shows a comparison of some industry equivalents in common TO247 packages. Silicon-based superjunction (Si SJ) devices and products from UnitedSiC can be driven from 0 to 10V drivers. SiC MOS options require different voltages (eg -4V to 18V). SiC devices all have lower input capacitance (gate charge) and greatly reduce diode recovery charge (Qrr). The parasitic diode conduction losses of silicon-based superjunctions and SiC FETs are lower than those of SiC MOSFETs.

Table 2: Parameter comparison of similar transistors in TO247 package

Table 3 shows a comparison of similar devices in a DFN8×8 footprint. Silicon based superjunctions, SiC FETs and GaN devices can all be driven by standard silicon gate drivers. UnitedSiC’s FET products have very low on-resistance. It is best to use the bottom three rows for performance characterization comparisons with different 150°C RDS(ON) device. The wide bandgap solution provides better performance characterization, especially for Rds*Coss(tr) and Rds*Qrr.

Table 3: Parameter comparison of silicon-based driver-compatible transistors in DFN8×8 package

Figure 4 shows cross-sectional architectures for common configurations of SiC FETs, GaN FETs, and silicon-based superjunction FETs. GaN HEMTs are lateral devices, while other device types are vertical devices. Vertical current flow enables higher voltage devices to be implemented more compactly because the source and drain terminals are located on opposite sides of the die rather than on the top surface. In GaN HEMTs, conduction is limited to two-dimensional electron gas (2DEG) channels, while SiC devices use short surface channels, but mostly for carrying current. SiC JFETs have a bulky channel and, combined with their vertical nature, have the lowest resistance per unit area (RdsA) and the smallest die size. The low voltage silicon MOSFETs are then cascaded (increasing the resistance by 10%) to form a SiC FET.

Figure 4: Architecture of competing semiconductor devices in the 650V space for data center power and telecom power

As the device improves, the ultimate switching speed limit is determined by the load current that charges the device output capacitor Coss. For a given on-resistance, a low value of Coss(tr) provides the fastest slew rate and the shortest delay time to 400V. It is evident from Table 3 that SiC FETs excel in this regard and are a good choice for high frequency power conversion.

In terms of Qrr, the wide-bandgap options have significantly improved performance compared to silicon-based superjunction devices. Therefore, these devices are selected whenever the circuit is turned on using hard switches as in a continuous current mode (CCM) totem-pole PFC. If these circuits conduct using parasitic diodes in the freewheeling state, the on-state voltage drop of the parasitic diodes will cause conduction losses. Therefore, synchronous conduction is often used, opening the FET channel to reduce these losses. There is usually a delay between detecting the current reversal and turning on the FET channel, and at high frequencies this time becomes a significant part of the switching cycle. For example, if the switching frequency is 100kHz (10us period), the dead time is 100ns, and diode conduction during this period does not matter. But during a switching period of 1MHz (1000ns period) it becomes 10%. Therefore, the low conduction voltage drop of the parasitic diode VSD and low Qrr are useful characteristics, and both are low for SiC FETs.

In addition, the most efficient circuit options avoid hard turn-on, because while the turn-off losses of wide-bandgap devices are negligible, turn-on losses are not. With the low gate charge, low on-resistance, and turn-off losses of the available FETs, the frequency of soft-switching circuits can be increased by a factor of 5-10.

In terms of device robustness, all SiC options have excellent avalanche capability, increasing the system reliability of the converter. Despite its small die size, it can often exceed the capabilities of superjunction FETs, especially at high current levels. GaN devices cannot handle avalanches and are designed with high breakdown voltages to avoid this operating region. Figure 5 shows the range of 80A peak avalanche current (blue) that a 40mohm, 650V SiC FET from UnitedSiC can withstand, well beyond any practical need. The observed breakdown voltage exceeds 800V (green).

Figure 5: Unclamped inductance test waveforms for the UF3C065040K4S (40mohm, 650V SiC FET device).Despite the small size of the SiC JFET, the device can withstand over 80A of avalanche current without failure

Gate Drive Considerations

A key simplification of using SiC FETs is that low voltage MOSFETs have a threshold voltage V of 5VTH and +/-25V maximum gate-source voltage VGS(MAX) rated value. It can be driven from 0 to 10V (or 12V) like a silicon-based superjunction MOSFET. Figure 6 is a comparison of the recommended gate drive voltages for various technologies and the corresponding gate absolute maximum ratings. SiC MOSFETs typically have negative and positive gate drives and require a total gate voltage swing of 20 to 25V. The gate voltage is usually very close to the absolute maximum ratings, which requires careful attention to gate spikes. Larger gate swings may add considerable gate charge losses at higher frequencies. Additionally, to manage the threshold voltage VTH Hysteresis issues, the manufacturer’s recommendations must be carefully followed to determine gate drive voltage levels. SiC FETs are very flexible in this regard, not only do they not require such careful control of gate voltage levels, but they can be driven at gate voltages that are compatible with SiC MOSFETs.

Figure 6: Graph comparing recommended gate drive and gate voltage maximum ratings for various silicon-based and SiC device types. SiC FETs are uniquely versatile

Enhancement-mode GaN devices typically have a lower threshold voltage Vthand is driven over a narrow gate voltage range, which is typically very close to the absolute maximum gate-source voltage VGS limit. This requires specialized drivers and careful layout to avoid damaging the switch. The cascode option avoids some of these difficulties. The lower gate voltage swing of enhancement mode devices is beneficial for reducing gate losses at higher frequencies.

In all cases, keeping the device off with high dV/dt becomes more and more challenging as the device is used at higher speeds. The same goes for the gate voltage spikes that manage the power loop and gate drive loop inductance. Using a package with Kelvin source pins would help a lot, but we’ll cover other options later in this article.

Circuit Topology CPFC Stage

Figure 7 shows the Totem Pole PFC (TPPFC) circuit and the measured efficiency at 100kHz using the UJC06505K type SiC FET on a 1.5KW UnitedSiC demo board. This circuit eliminates all diode conduction losses from the input diode bridge and SiC PFC diodes. In this case, the converter operates in continuous current mode (CCM) and hard switches the device.

Figure 7: Basic totem-pole PFC circuit, and efficiency data compared to titanium gold standard, measured on UnitedSiC’s demo board using the UJC06505K type SiC FET

Figure 8 shows an interleaved TPPFC that can be used with coupled inductors at design time. The circuit can be used in continuous current mode or at a higher frequency in critical conduction mode, as turn-on losses are eliminated. Using SiC FETs enables very high power densities without sacrificing efficiency, albeit with higher control and magnetic design complexity where ripple currents are high and current zero-crossings must be detected.

Figure 8: Interleaved totem-pole PFC with two fast switches and a line-frequency switching half-bridge.Coupled-inductor approach allows operation in critical conduction mode, which can significantly increase frequency

Table 4 shows a comparison of the loss breakdown using the interleaved PFC topology shown in Figure 1 and the interleaved totem-pole PFC of Figure 8. In both cases, we assume a 3KW converter running each switch at 100kHz. Interleaving means the inductor has a ripple frequency of 200kHz. The loss of the totem-pole PFC is reduced by 25.7W (vs. 51.4A), allowing the net efficiency target of the titanium standard to be achieved. This is achieved by eliminating the 24.3W losses of the bridge rectifier. The totem-pole PFC used in this example requires more than four FETs and gate drives.

Table 4: Loss and complexity comparison of interleaved PFC and totem-pole PFC circuits for 3KW at 100kHz using UJC06505K in CCM mode

Another method that does not require detection of current crossovers is to use an additional auxiliary switch to achieve zero-voltage switching when turned on. Using resonant techniques such as Auxiliary Resonant Transforming Pole (ARCP) can eliminate turn-on and turn-off losses for similar or better results. However, more advanced technology has a cost-effectiveness advantage only at power levels well above 5KW.

Circuit Topology C DC-DC Stage

Because the output voltage is fixed, the full-bridge LLC converter of Figure 1 provides excellent power density and efficiency and is now an industry workhorse for high power level applications. As power is reduced, a half-bridge LLC implementation can be employed. The common frequency range is 100-500kHz, and considering the high current level of the 12V output, the key work of reducing losses is shifted to the transformer secondary MOSFET and the low voltage secondary MOSFET.

For high voltage FETs, the drain-source voltage VDS The output capacitor needs to be charged in the transition from its off state to the diode conducting, and for fast charging, COSS(TR) must be low. However, the user must minimize the dead time before synchronous conduction of the FET gate to reduce parasitic diode conduction losses. Low resistance in the on state minimizes conduction losses, the off energy E for most superjunction and wide bandgap switchesOFF low to help keep switching losses to a minimum.

Diode hard recovery can occur if ZVS is lost under light load conditions. For wide-bandgap switches such as SiC FETs, this poses no risk, but can damage silicon-based superjunction MOSFETs. To minimize this possibility, fast-recovery versions of superjunction FETs are often used, but such precautions are not required for SiC FETs.

near-term outlook

While improvements in silicon-based superjunction FETs continue, the level of improvement possible in SiC and GaN devices over the next few years will far exceed what can be achieved with silicon devices. In addition to improving the resistance per unit area RdsA (30-50% increase every 2-3 years), many improvements in packaging technology are expected. The main challenge to solve is how to dissipate heat more efficiently in low inductance and small surface mount options.

One possible route is to upgrade to half-bridge components designed for direct surface mount use or as embedded components in circuit boards. This simplifies board layout and allows for lower inductive power and gate loops.

Another emerging avenue for driver integration with power devices is as a single driver plus switch or as a half-bridge element. Since most SiC devices and GaN devices require unique drive voltage levels and circuitry, this complexity can be absorbed into co-packaged or integrated products, making it easier for users. In addition, each device can then be better utilized to its full potential. Undoubtedly, this will further save system cost and power consumption and drive the adoption of wide bandgap devices.

Along these lines, previous articles in this series presented a SIP half-bridge with an integrated half-bridge gate driver using a 35mohm, 1200V SiC FET. Many suppliers are offering surface mount options, and this trend is likely to accelerate.

The cost of 650V wide bandgap switches is now falling rapidly. UnitedSiC’s 650V FETs are expected to be priced close to silicon devices within the next two years. Along with ease of use, this trend is expected to rapidly accelerate the deployment of wide-bandgap devices in server and telecom power supply applications.